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    SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES
    11.
    发明申请
    SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES 审中-公开

    公开(公告)号：US20170141078A1

    公开(公告)日：2017-05-18

    申请号：US15416447

    申请日：2017-01-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anson J. Call ,  Erwin B. Cohen ,  Dany Minier ,  Wolfgang Sauter ,  David B. Stone ,  Eric W. Tremble

    IPC: H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L25/00

    Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

    Connected plane stiffener within integrated circuit chip carrier
    12.
    发明授权
    Connected plane stiffener within integrated circuit chip carrier 有权

    公开(公告)号：US10770385B2

    公开(公告)日：2020-09-08

    申请号：US16046653

    申请日：2018-07-26

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Brian W. Quinlan ,  Krishna R. Tunga

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/10 ,  H01L23/053 ,  H01L23/367

    Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

    Connected Plane Stiffener Within Integrated Circuit Chip Carrier
    13.
    发明申请
    Connected Plane Stiffener Within Integrated Circuit Chip Carrier 审中-公开

    公开(公告)号：US20200035593A1

    公开(公告)日：2020-01-30

    申请号：US16046653

    申请日：2018-07-26

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Brian W. Quinlan ,  Krishna R. Tunga

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

    Reduction of solder interconnect stress
    15.
    发明授权
    Reduction of solder interconnect stress 有权

    公开(公告)号：US10276534B2

    公开(公告)日：2019-04-30

    申请号：US15671955

    申请日：2017-08-08

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

    LAMINATE SUBSTRATE THERMAL WARPAGE PREDICTION FOR DESIGNING A LAMINATE SUBSTRATE
    17.
    发明申请
    LAMINATE SUBSTRATE THERMAL WARPAGE PREDICTION FOR DESIGNING A LAMINATE SUBSTRATE 审中-公开

    公开(公告)号：US20170351783A1

    公开(公告)日：2017-12-07

    申请号：US15176101

    申请日：2016-06-07

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

    IPC: G06F17/50 ,  G06F17/13

    CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F2217/44 ,  G06F2217/80

    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.

    Laminate substrate thermal warpage prediction for designing a laminate substrate
    19.
    发明授权
    Laminate substrate thermal warpage prediction for designing a laminate substrate 有权

    公开(公告)号：US10108753B2

    公开(公告)日：2018-10-23

    申请号：US15176101

    申请日：2016-06-07

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

    IPC: G06F17/50

    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.

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