公开(公告)号：US11239183B2

公开(公告)日：2022-02-01

申请号：US16779529

申请日：2020-01-31

Applicant: International Business Machines Corporation

Inventor： Tuhin Sinha ,  Krishna R. Tunga ,  Brian W. Quinlan ,  Charles Leon Arvin ,  Steven Paul Ostrander ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/14 ,  H01L21/48 ,  H01L23/66 ,  H01L23/538

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

公开(公告)号：US10916154B2

公开(公告)日：2021-02-09

申请号：US15793519

申请日：2017-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mahmoud Amin ,  Zhenxing Bi ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Christopher J. Penny ,  Krishna R. Tunga ,  Loma Vaishnav

IPC: G09B5/02 ,  G09B19/04 ,  G10L15/26 ,  G09B19/06 ,  G06F16/40 ,  G06F40/40

Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning.

公开(公告)号：US10756031B1

公开(公告)日：2020-08-25

申请号：US16409321

申请日：2019-05-10

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Franklin M. Baez ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/34 ,  H01L23/64 ,  H01L49/02 ,  H01L23/04 ,  H01L23/522

Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.

公开(公告)号：US20200051447A1

公开(公告)日：2020-02-13

申请号：US16100621

申请日：2018-08-10

Applicant: International Business Machines Corporation

Inventor： Krishna R. Tunga ,  Lawrence A. Clevenger ,  Stefania Axo ,  Mark C. Wallen ,  Yang Liu ,  Shidong Li ,  Bryan Gury

IPC: G09B5/02 ,  G06K9/62 ,  G06F15/18 ,  G06N3/02

Abstract: Provided are systems, methods, and media for teaching generalization of an object. An example method includes obtaining a set of traits of an object recognized by a person in an input image, in which a subset of traits are traits fixated on by the person when recognizing the object in the input image. Executing a machine learning algorithm to generate a set of generalized images of the object. Each generalized image is generated with at least one trait of being modified, in which the set of generalized images are ordered in a sequence based on proximity of each of the generalized images to the input image. Presenting at least a first generalized image to the person in accordance with the sequence. Modifying the order of the generalized images in the sequence in response to detecting from feedback that the person does not recognize the object in the first generalized image.

公开(公告)号：US10426400B2

公开(公告)日：2019-10-01

申请号：US15631064

申请日：2017-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mahmoud Amin ,  Zhenxing Bi ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Krishna R. Tunga

IPC: A61B5/00 ,  G16H50/20 ,  G16H15/00 ,  G16H20/30 ,  G16H10/60 ,  G16H40/63 ,  A61B5/11

Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.

公开(公告)号：US10424527B2

公开(公告)日：2019-09-24

申请号：US15812290

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Hilton T. Toy ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/00 ,  H01L23/10 ,  H01L23/053

Abstract: An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.

公开(公告)号：US20180061799A1

公开(公告)日：2018-03-01

申请号：US15671955

申请日：2017-08-08

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/17133 ,  H01L2924/3512

Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

公开(公告)号：US11784160B2

公开(公告)日：2023-10-10

申请号：US17030360

申请日：2020-09-23

Applicant: International Business Machines Corporation

Inventor： Katsuyuki Sakuma ,  Krishna R. Tunga ,  Shidong Li ,  Griselda Bonilla

IPC: H01L23/00 ,  H01L21/48

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13023 ,  H01L2224/14132 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203

Abstract: An integrated circuit package substrate (ICPS) system includes a die including a first array of connectors and a substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature. The first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center, and the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center.

公开(公告)号：US11545444B2

公开(公告)日：2023-01-03

申请号：US17139313

申请日：2020-12-31

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  Katsuyuki Sakuma ,  Krishna R. Tunga ,  Hilton T. Toy

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A lidded chip package apparatus has reduced latent thermal stress in an under-chip high-CTE layer of the chip package because the lid of the package was adhered to a substrate of the package and cured during a same thermal excursion as when underfill was dispensed and cured under a chip of the package, and the chip package was cooled from the combined underfill and lidding process to room temperature with the lid adhered to the chip and the substrate, thereby reducing latent thermal stress in the under-chip high-CTE layer of the chip package.

公开(公告)号：US20220208693A1

公开(公告)日：2022-06-30

申请号：US17139313

申请日：2020-12-31

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  Katsuyuki Sakuma ,  Krishna R. Tunga ,  Hilton T. Toy

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A lidded chip package apparatus has reduced latent thermal stress in an under-chip high-CTE layer of the chip package because the lid of the package was adhered to a substrate of the package and cured during a same thermal excursion as when underfill was dispensed and cured under a chip of the package, and the chip package was cooled from the combined underfill and lidding process to room temperature with the lid adhered to the chip and the substrate, thereby reducing latent thermal stress in the under-chip high-CTE layer of the chip package.