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    Semiconductor package via stack checking
    1.
    发明授权
    Semiconductor package via stack checking 有权

    公开(公告)号：US10546096B2

    公开(公告)日：2020-01-28

    申请号：US15719693

    申请日：2017-09-29

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Paul R. Walling

    IPC: G06F17/50

    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.

    REDUCTION OF SOLDER INTERCONNECT STRESS
    2.
    发明申请
    REDUCTION OF SOLDER INTERCONNECT STRESS 审中-公开

    公开(公告)号：US20180061799A1

    公开(公告)日：2018-03-01

    申请号：US15671955

    申请日：2017-08-08

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/17133 ,  H01L2924/3512

    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

    Semiconductor package metal shadowing checks
    5.
    发明授权
    Semiconductor package metal shadowing checks 有权

    公开(公告)号：US10956649B2

    公开(公告)日：2021-03-23

    申请号：US16547623

    申请日：2019-08-22

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

    IPC: G06F30/398 ,  G06F30/394 ,  G06F111/10 ,  G06F113/18 ,  G06F113/20

    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

    SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS
    6.
    发明申请
    SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS 审中-公开

    公开(公告)号：US20190102506A1

    公开(公告)日：2019-04-04

    申请号：US15719743

    申请日：2017-09-29

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/16 ,  G06F2217/38 ,  G06F2217/40

    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

    Semiconductor package metal shadowing checks
    8.
    发明授权
    Semiconductor package metal shadowing checks 有权

    公开(公告)号：US10423752B2

    公开(公告)日：2019-09-24

    申请号：US15719743

    申请日：2017-09-29

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

    IPC: G06F17/50

    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

    SEMICONDUCTOR PACKAGE VIA STACK CHECKING
    10.
    发明申请
    SEMICONDUCTOR PACKAGE VIA STACK CHECKING 审中-公开

    公开(公告)号：US20190102504A1

    公开(公告)日：2019-04-04

    申请号：US15719693

    申请日：2017-09-29

    Applicant: International Business Machines Corporation

    Inventor： Anson J. Call ,  Paul R. Walling

    IPC: G06F17/50

    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.

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