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公开(公告)号：US20210118947A1
公开(公告)日：2021-04-22
申请号：US17137996
申请日：2020-12-30
摘要： A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.
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公开(公告)号：US20200043978A1
公开(公告)日：2020-02-06
申请号：US16051457
申请日：2018-07-31
摘要： A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.
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公开(公告)号：US20230088757A1
公开(公告)日：2023-03-23
申请号：US17483216
申请日：2021-09-23
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02
摘要： A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.
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公开(公告)号：US20220301942A1
公开(公告)日：2022-09-22
申请号：US17204016
申请日：2021-03-17
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66
摘要： A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.
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公开(公告)号：US11270999B2
公开(公告)日：2022-03-08
申请号：US17224258
申请日：2021-04-07
IPC分类号： H01L27/108 , G11C11/404 , G11C11/401
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US11183978B2
公开(公告)日：2021-11-23
申请号：US16433163
申请日：2019-06-06
发明人： Cezar Bogdan Zota , Lukas Czornomaz
IPC分类号： H03F3/193 , G06N10/00 , H01L29/775 , H01L29/778 , H03F1/30 , H03F1/52 , H03F3/21
摘要： An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.
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公开(公告)号：US10892299B2
公开(公告)日：2021-01-12
申请号：US16051457
申请日：2018-07-31
摘要： A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.
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