公开(公告)号：US20210020743A1

公开(公告)日：2021-01-21

申请号：US16515143

申请日：2019-07-18

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Tenko Yamashita ,  Guillaume Audoit ,  Nicolas Bernier ,  Remi Coquand ,  Shay Reboh

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

公开(公告)号：US20200098859A1

公开(公告)日：2020-03-26

申请号：US16580396

申请日：2019-09-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  International Business Machines Corporation

Inventor： Shay Reboh ,  Remi Coquand ,  Nicolas Loubet ,  Tenko Yamashita ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/775 ,  H01L27/088 ,  H01L29/76 ,  H01L29/66 ,  H01L27/06

Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.

公开(公告)号：US10553723B2

公开(公告)日：2020-02-04

申请号：US16054524

申请日：2018-08-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Remi Coquand ,  Nicolas Loubet ,  Shay Reboh ,  Robin Chao

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/225 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/66

Abstract: A method is provided of fabricating a microelectronic device including a semiconductor structure provided with semiconductor bars positioned above one another, the method including the following steps: creating, on a substrate, a stacked structure including an alternation of first bars containing a first material and having a first critical dimension and second bars containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions of the second bars before forming a source and drain block on the portions.

公开(公告)号：US10431683B2

公开(公告)日：2019-10-01

申请号：US15837281

申请日：2017-12-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161

Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.

公开(公告)号：US20250089288A1

公开(公告)日：2025-03-13

申请号：US18465247

申请日：2023-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Julien Frougier ,  Shay Reboh

IPC: H01L29/775 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: According to the embodiment of the present invention, a semiconductor device includes a plurality of nanodevices including a plurality of transistors. The plurality of nanodevices are located adjacent to and parallel to each other along an x-axis. A gate contact is located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices. The gate contact includes a recessed portion. A backside gate cut dielectric pillar extends downwards through the recessed portion to be in direct contact with the gate contact.

公开(公告)号：US20250056865A1

公开(公告)日：2025-02-13

申请号：US18366083

申请日：2023-08-07

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Shay Reboh ,  Julien Frougier ,  Ruilong Xie

IPC: H01L29/417 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor structure includes a front-end-of-line level formed by a plurality of field effect transistors. Each field effect transistor includes a source/drain region disposed on opposite sides of the field effect transistor. A metal contact region is disposed above and in contact with a first surface of two adjacent source/drain regions. Each of the two adjacent source/drain regions correspond to a field effect transistor. A backside isolation region cuts through the metal contact region from a backside of the plurality of field effect transistors for electrically isolating the two adjacent source/drain regions.

公开(公告)号：US20210257450A1

公开(公告)日：2021-08-19

申请号：US17240002

申请日：2021-04-26

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Tenko Yamashita ,  Guillaume Audoit ,  Nicolas Bernier ,  Remi Coquand ,  Shay Reboh

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

公开(公告)号：US10714392B2

公开(公告)日：2020-07-14

申请号：US16038985

申请日：2018-07-18

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Emmanuel Augendre ,  Remi Coquand ,  Shay Reboh

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/306

Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

公开(公告)号：US20200027791A1

公开(公告)日：2020-01-23

申请号：US16038985

申请日：2018-07-18

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Emmanuel Augendre ,  Remi Coquand ,  Shay Reboh

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

公开(公告)号：US20250087527A1

公开(公告)日：2025-03-13

申请号：US18466783

申请日：2023-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prabudhya Roy Chowdhury ,  Daniel Charles Edelstein ,  Shay Reboh

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor device includes a device wafer, including a silicon wafer. A handler wafer is bonded to the device wafer. The handler wafer includes a 111 crystallographic direction silicon substrate.