公开(公告)号：US20250040240A1

公开(公告)日：2025-01-30

申请号：US18361255

申请日：2023-07-28

Applicant: International Business Machines Corporation

Inventor： Shay Reboh ,  Julien Frougier ,  Leon Sigal ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

公开(公告)号：US20250151342A1

公开(公告)日：2025-05-08

申请号：US18502125

申请日：2023-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Ruilong Xie ,  Shay Reboh ,  Junli Wang

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first group of field-effect-transistors (FETs); a second group of FETs on top of the first group of FETs; a first half-single-diffusion-break (H-SDB) underneath and being separated from one of the FETs of the second group by a middle-dielectric-insulator (MDI) layer; and a second H-SDB on top of and being separated from one of the FETs of the first group by the MDI layer, where the first H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs, and the second H-SDB insulates a S/D region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs. A method of forming the same is also provided.

公开(公告)号：US20250133816A1

公开(公告)日：2025-04-24

申请号：US18489056

申请日：2023-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  Shay Reboh ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

公开(公告)号：US11575003B2

公开(公告)日：2023-02-07

申请号：US17240002

申请日：2021-04-26

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Tenko Yamashita ,  Guillaume Audoit ,  Nicolas Bernier ,  Remi Coquand ,  Shay Reboh

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

公开(公告)号：US11088247B2

公开(公告)日：2021-08-10

申请号：US16812530

申请日：2020-03-09

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  International Business Machines Corporation

Inventor： Shay Reboh ,  Kangguo Cheng ,  Remi Coquand ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/76 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.

公开(公告)号：US11081547B2

公开(公告)日：2021-08-03

申请号：US16580396

申请日：2019-09-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  International Business Machines Corporation

Inventor： Shay Reboh ,  Remi Coquand ,  Nicolas Loubet ,  Tenko Yamashita ,  Jingyun Zhang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775

Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.

公开(公告)号：US20250157886A1

公开(公告)日：2025-05-15

申请号：US18507181

申请日：2023-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Jianwei Peng ,  Shay Reboh ,  Brent A. Anderson ,  Nicholas Alexander POLOMOFF

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor component includes a backside contact. The semiconductor component further includes two inactive transistor gates each associated with a region of source/drain material of a respective transistor. The region of source/drain material of at least one of the transistors is in direct contact with the backside contact. The semiconductor component further includes a diffusion break formed between the two inactive transistor gates and made of a dielectric material. The diffusion break extends from a lowermost surface that is substantially coplanar with a lowermost surface of the backside contact to an uppermost surface that is substantially coplanar with an uppermost surface of the region of source/drain material of at least one of the inactive transistor gates.

公开(公告)号：US20250048688A1

公开(公告)日：2025-02-06

申请号：US18228261

申请日：2023-07-31

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Shay Reboh ,  John Christopher Arnold ,  Indira Seshadri ,  Chen Zhang ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device including stacked field effect transistors (FETs) is provided. The stacked FETs are formed utilizing a process that optimizes the thermal budget without negatively impacting the frontside and/or backside contact structures. The stacked can be designed to have different work function metals and a frontside/backside deep via structure can be provided that has a low area resistance.

公开(公告)号：US20250006730A1

公开(公告)日：2025-01-02

申请号：US18342090

申请日：2023-06-27

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Shay Reboh ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.

公开(公告)号：US11049933B2

公开(公告)日：2021-06-29

申请号：US16515143

申请日：2019-07-18

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Tenko Yamashita ,  Guillaume Audoit ,  Nicolas Bernier ,  Remi Coquand ,  Shay Reboh

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.