公开(公告)号：US11462583B2

公开(公告)日：2022-10-04

申请号：US16672752

申请日：2019-11-04

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Daniel Charles Edelstein ,  John Arnold ,  Theodorus E. Standaert

IPC: H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L43/02

Abstract: A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.

公开(公告)号：US20220277964A1

公开(公告)日：2022-09-01

申请号：US17186064

申请日：2021-02-26

Applicant: International Business Machines Corporation

Inventor： Mahadevaiyer Krishnan ,  Michael Francis Lofaro ,  Andrew Giannetta ,  Douglas Bishop ,  Eugene J. O'Sullivan ,  Daniel Charles Edelstein

IPC: H01L21/321 ,  H01L21/768 ,  C09G1/02

Abstract: A method for planarizing a metal conductor layer embedded in a dielectric layer is provided. The method includes removing a portion of an overburden of the metal conductor layer that is formed over the dielectric layer with a first CMP slurry. The method also includes removing a remaining portion of the overburden of the metal conductor layer with a second CMP slurry to expose upper portions of the dielectric layer.

公开(公告)号：US20210296118A1

公开(公告)日：2021-09-23

申请号：US16824559

申请日：2020-03-19

Applicant: International Business Machines Corporation

Inventor： Devika Sil ,  Ashim Dutta ,  Yann Mignot ,  John Christopher Arnold ,  Daniel Charles Edelstein ,  Kedari Matam ,  Cornelius Brown Peethala

IPC: H01L21/02 ,  H01L21/3065

Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer; and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

公开(公告)号：US11031542B2

公开(公告)日：2021-06-08

申请号：US16401206

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.

公开(公告)号：US20210013400A1

公开(公告)日：2021-01-14

申请号：US16506459

申请日：2019-07-09

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

公开(公告)号：US20250169145A1

公开(公告)日：2025-05-22

申请号：US18516002

申请日：2023-11-21

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Su Chen Fan ,  Ruilong Xie ,  Kisik Choi ,  Miaomiao Wang ,  Daniel Charles Edelstein

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure includes a field effect transistor having a plurality of source/drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source/drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source/drain region of the plurality of source/drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source/drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

公开(公告)号：US20240395822A1

公开(公告)日：2024-11-28

申请号：US18322620

申请日：2023-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Daniel Charles Edelstein ,  Lawrence A. Clevenger

IPC: H01L27/12 ,  H01L21/84

Abstract: A microelectronic structure including a first nanosheet transistor including a first backside metal line that has a first width as measure along a bottom surface of the first backside metal line and the first backside metal line has a second width as measure along a top surface of the first backside metal line. A second backside metal line that includes a second backside contact that is connected to the second source drain and the second backside metal line has a third width as measure along a bottom surface of the second backside metal line. The second backside metal line has a fourth width as measure along a top surface of the second backside metal line. The first width is larger than the second width and the third width is larger than the fourth width.

公开(公告)号：US20230189671A1

公开(公告)日：2023-06-15

申请号：US17550200

申请日：2021-12-14

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: H01L45/00 ,  H01L27/11507 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L45/1253 ,  H01L27/11507 ,  H01L27/222 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/12 ,  H01L45/1233 ,  H01L45/1675

Abstract: A semiconductor device and formation thereof. The semiconductor device includes a memory device located on top of a first bottom interconnect, wherein the first bottom interconnect is embedded in a first dielectric layer. The semiconductor device further includes a second bottom interconnect embedded in the first dielectric layer, wherein the second bottom interconnect is adjacent to the first bottom interconnect. A top surface of the second bottom interconnect is recessed relative to a top surface of the first bottom interconnect.

公开(公告)号：US20210320060A1

公开(公告)日：2021-10-14

申请号：US16842951

申请日：2020-04-08

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Chih-Chao Yang ,  Daniel Charles Edelstein

IPC: H01L23/522 ,  H01L21/768 ,  H01L43/12

Abstract: A via structure and methods for forming a via structure generally includes a via opening in a dielectric layer. A conformal barrier layer is in the via opening; and a conductive metal on the barrier layer in the via opening. The conductive metal includes a recessed top surface. A conductive planarization stop layer is on the recessed top surface and extends about a shoulder portion formed in the dielectric layer, wherein the shoulder portion extends about a perimeter of the via opening. A fill material including an insulator material or a conductor material is on the conductive planarization stop layer within the recessed top surface, wherein the conductive planarization stop layer on the shoulder portion is coplanar to the insulator material or the conductor material. Also described are methods of fabricating the via structure.

公开(公告)号：US20210183627A1

公开(公告)日：2021-06-17

申请号：US16710232

申请日：2019-12-11

Applicant: International Business Machines Corporation

Inventor： John Arnold ,  Donald Canaperi ,  Cornelius Brown Peethala ,  Daniel Charles Edelstein

IPC: H01J37/32 ,  H01J37/305 ,  H01L21/683 ,  H01L21/67

Abstract: An ion beam etching tool comprises a chuck configured to electrostatically receive a wafer; a plasma source configured to introduce an ion beam to the wafer; and a shield on the chuck and configured to shield the chuck from the ion beam. The shield comprises a material that is configured to be one of removable from the wafer or inert with regard to a semiconductor device on the wafer.