Coherent interconnects between superconducting qubits and microwave-optical transducers

    公开(公告)号:US12191051B2

    公开(公告)日:2025-01-07

    申请号:US18329743

    申请日:2023-06-06

    Abstract: Systems and techniques that facilitate enabling transfer of a quantum state between a quantum device and a microwave resonator of a microwave optical transducer. In various embodiments, a system can comprise a quantum device, a microwave optical transducer including a microwave resonator, and a coherent interconnect. In various embodiments, the coherent interconnect can be between the quantum device and the microwave optical transducer that can enable bi-directional transfer of a quantum state between the quantum device and the microwave resonator. In various embodiments, the microwave optical transducer can be separately packaged from the quantum device. With various embodiments, the coherent interconnect can be a superconducting coaxial cable.

    CRYOGENIC FILTER MODULES FOR SCALABLE QUANTUM COMPUTING ARCHITECTURES

    公开(公告)号:US20240070506A1

    公开(公告)日:2024-02-29

    申请号:US17822499

    申请日:2022-08-26

    CPC classification number: G06N10/40

    Abstract: One or more systems, devices, and/or methods of use provided herein relate to signal filters for scalable quantum computing architectures. According to one embodiment, a device can comprise a circuit board comprising a plurality of layers, wherein various ones of the plurality of layers comprises a different absorptive material, and a plurality of signal lines that pass through the circuit board, wherein a first layer of the circuit board is comprised of a first material that filters a first signal line that traverses through at least the first layer of the plurality of layers.

    TRIMMABLE INDUCTORS FOR QUBIT FREQUENCY TUNING

    公开(公告)号:US20220293845A1

    公开(公告)日:2022-09-15

    申请号:US17200487

    申请日:2021-03-12

    Abstract: Systems and techniques that facilitate trimmable inductors for qubit frequency tuning are provided. In various embodiments, a device can comprise a Josephson junction. In various aspects, the Josephson junction can be shunted by a capacitor, and a trimmable inductor can couple the Josephson junction to a pad of the capacitor. In various cases, the trimmable inductor can comprise a first conductive path that includes a severable and/or weldable superconducting bridge and a second conductive path that is in parallel with the first conductive path. In various aspects, severing and/or welding the severable and/or weldable superconducting bridge can controllably change an inductance of the trimmable inductor, which can commensurately change a resonant frequency of a qubit formed by the Josephson junction and the capacitor.

    CURRENT BIASED TUNABLE QUBIT
    15.
    发明申请

    公开(公告)号:US20220094358A1

    公开(公告)日:2022-03-24

    申请号:US17031369

    申请日:2020-09-24

    Inventor: Timothy Phung

    Abstract: Techniques for designing, creating, and utilizing a current biased tunable qubit are presented. A qubit device can comprise a first Josephson junction (JJ) located along a first current path of the device, and a second JJ and third JJ coupled in series along a second current path in parallel with the first current path, wherein the second and third JJs facilitate controlling frequency of the device. The first JJ can be larger in area than each of the second and third JJs, wherein a current splitting ratio between the first current path and second current path can be increased thereby. The device can comprise a capacitor with a first terminal associated with the second and third JJs, and a second terminal associated with ground. Alternatively, a high kinetic inductance wire can be used in the first current path, instead of the JJ.

    High connectivity parametric gate
    17.
    发明授权

    公开(公告)号:US12015397B2

    公开(公告)日:2024-06-18

    申请号:US17820721

    申请日:2022-08-18

    Inventor: Timothy Phung

    CPC classification number: H03K17/92 G06N10/40 H10N60/12 H10N69/00

    Abstract: One or more systems, devices, and/or methods of manufacture and/or use provided herein relate to a quantum computing process to achieve higher connectivity of qubits to more than nearest neighbors and/or to a plurality of nearest neighbors. A system can comprise a tunable first coupler coupled to a first qubit, a tunable second coupler coupled to a second qubit, and a junction coupling the first coupler and the second coupler being both parametrically drivable. The first coupler and the second coupler can comprise superconducting quantum interference devices or Josephson junctions. The junction can comprise a central hub or central node separately coupled to the first coupler and the second coupler. The first coupler and the second coupler can be configured to capacitively or inductively couple the first qubit and the second qubit to one another to perform a control-Z (CZ) gate or an iSWAP gate.

    HIGH CONNECTIVITY PARAMETRIC GATE
    18.
    发明公开

    公开(公告)号:US20240063791A1

    公开(公告)日:2024-02-22

    申请号:US17820721

    申请日:2022-08-18

    Inventor: Timothy Phung

    CPC classification number: H03K17/92 G06N10/40 H01L39/223 H01L27/18

    Abstract: One or more systems, devices, and/or methods of manufacture and/or use provided herein relate to a quantum computing process to achieve higher connectivity of qubits to more than nearest neighbors and/or to a plurality of nearest neighbors. A system can comprise a tunable first coupler coupled to a first qubit, a tunable second coupler coupled to a second qubit, and a junction coupling the first coupler and the second coupler being both parametrically drivable. The first coupler and the second coupler can comprise superconducting quantum interference devices or Josephson junctions. The junction can comprise a central hub or central node separately coupled to the first coupler and the second coupler. The first coupler and the second coupler can be configured to capacitively or inductively couple the first qubit and the second qubit to one another to perform a control-Z (CZ) gate or an iSWAP gate.

    MECHANICALLY TOLERANT COUPLERS
    19.
    发明公开

    公开(公告)号:US20230359918A1

    公开(公告)日:2023-11-09

    申请号:US17740292

    申请日:2022-05-09

    CPC classification number: G06N10/40

    Abstract: A modular electronic structure includes a first chip having a first interleaved portion and a first electromagnetic coupler on the first interleaved portion. There is a second chip having a second interleaved portion and a second electromagnetic coupler on the second interleaved portion and configured to electromagnetically couple with the first electromagnetic coupler. The first interleaved portion fits between two surfaces of the second chip. The second interleaved portion fits between two surfaces of the first chip.

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