公开(公告)号：US20160342723A1

公开(公告)日：2016-11-24

申请号：US14717026

申请日：2015-05-20

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K1/0265 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0979

Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

公开(公告)号：US20160150638A1

公开(公告)日：2016-05-26

申请号：US14551185

申请日：2014-11-24

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08

CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。

公开(公告)号：US10943044B2

公开(公告)日：2021-03-09

申请号：US15806397

申请日：2017-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhaoqing Chen

IPC: G06F30/367 ,  G06F111/10

Abstract: Embodiments of the present invention are directed to a computer-implemented method of simulating forward traveling voltages in a simulated circuit. The method includes inserting a traveling wave probe, via a processor, at an observation point of a simulated transmission line. The processor applies a first signal at an input of the traveling wave probe, and evaluates an output of the traveling wave probe. The processor next determines an instantaneous wave forward voltage and an instantaneous wave backward voltage at the traveling wave probe, and displays the instantaneous wave forward voltage and the instantaneous wave backward voltage via an output device.

公开(公告)号：US20180349536A1

公开(公告)日：2018-12-06

申请号：US15613448

申请日：2017-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhaoqing Chen

IPC: G06F17/50

Abstract: Embodiments of the present invention are directed to a computer-implemented method of simulating forward traveling voltages in a simulated circuit. The method includes inserting a traveling wave probe, via a processor, at an observation point of a simulated transmission line. The processor applies a first signal at an input of the traveling wave probe, and evaluates an output of the traveling wave probe. The processor next determines an instantaneous wave forward voltage and an instantaneous wave backward voltage at the traveling wave probe, and displays the instantaneous wave forward voltage and the instantaneous wave backward voltage via an output device.

公开(公告)号：US20170091362A1

公开(公告)日：2017-03-30

申请号：US14864953

申请日：2015-09-25

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/36

Abstract: A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.

公开(公告)号：US09594865B2

公开(公告)日：2017-03-14

申请号：US14717026

申请日：2015-05-20

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: G06F17/50 ,  H05K3/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K1/0265 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0979

Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

Abstract translation: 一个方面是一种方法，其包括通过在电路设计系统的处理器上执行的电力通过放置工具来识别基于设计文件的多层电路板的电压域的源极和接收器，该设计文件定义了 多层电路板。 确定支持从源到汇的最大电流需求的多个电源通孔。 在多层电路板的位置处确定多个电源通孔的位置，该位置通过源极和漏极之间的电力通孔形成通路，并具有基本上相等的总路径长度，通过在源极和漏极之间限定的每个总路径 通过至少一个电源通孔。 设计文件被修改为在位置包括电源通孔。

公开(公告)号：US09542516B1

公开(公告)日：2017-01-10

申请号：US15047667

申请日：2016-02-19

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/36

Abstract: A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.

Abstract translation: 提供了一种生成减少延迟双轴SPICE模型的方法。 该方法可以包括测量双轴电缆的近端S参数分量和远端S参数分量，通过将每个远端S参数乘以来减少远端S参数分量的原始时间延迟 通过基于等效延迟长度，信号频率和有效介电常数的复数指数的分量，通过使用近端S参数分量运行4端口SPICE模型来模拟通过双轴电缆传输的信号，并乘以 远端S参数分量，并且将相对于频率的发射信号的幅度和相位记录为减小延迟双轴SPICE模型的输出。

公开(公告)号：US20170004923A1

公开(公告)日：2017-01-05

申请号：US14755551

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U Mandrekar ,  Tingdong Zhou

IPC: H01G4/06 ,  G06F17/50 ,  H01G13/00

CPC classification number: G06F17/5072 ,  G06F2217/82 ,  H01G4/06 ,  H01G4/224 ,  H01G13/00 ,  H05K1/0231 ,  H05K1/162

Abstract: In one embodiment, a method includes positioning a first signal pad in a first layer of a printed circuit board and positioning a second signal pad in a second layer of the printed circuit board. The second signal pad is positioned to form an embedded capacitance between the first signal pad and the second signal pad. The embedded capacitance between the first signal pad and the second signal pad is configured to carry a signal between the first layer and the second layer absent a signal via.

Abstract translation: 在一个实施例中，一种方法包括将第一信号焊盘定位在印刷电路板的第一层中，并将第二信号焊盘定位在印刷电路板的第二层中。 定位第二信号垫以在第一信号焊盘和第二信号焊盘之间形成嵌入的电容。 第一信号焊盘和第二信号焊盘之间的嵌入电容被配置为在没有信号通孔的情况下在第一层和第二层之间传送信号。

公开(公告)号：US09984188B2

公开(公告)日：2018-05-29

申请号：US15047002

申请日：2016-02-18

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077

Abstract: A method of forming a mixed mode response from a single ended mode input includes modeling a first voltage controlled current source based on relative values of a vpositive input signal and a vnegative input signal and modeling a second voltage controlled current source based on relative values of the vpositive input signal and the vnegative input signal. A method of forming a single ended mode response from a mixed mode input modeling a first voltage controlled current source based on relative values of a vDIFFin input signal and a vCOMMin input signal and modeling a second voltage controlled current source based on relative values of the vDIFFin input signal and the vCOMMin input signal, the second voltage controlled being connected to ground through a second terminating impedance that is equal to the reference impedance (Z0).

公开(公告)号：US09972566B2

公开(公告)日：2018-05-15

申请号：US15336884

申请日：2016-10-28

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: H01L23/498 ,  H01L23/528 ,  H04B3/32 ,  H01P3/02 ,  H01P3/08 ,  H05K1/02 ,  H04B1/00 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.