公开(公告)号：US10530422B2

公开(公告)日：2020-01-07

申请号：US15047011

申请日：2016-02-18

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: H04B3/46

Abstract: A method of analyzing a transient response of an electronic circuit includes receiving at a jitter modulator circuit first and second input signals, modulating the second input signal on the first input signal in the jitter modulator circuit and outputting a modulated signal based on the first and second input signals. The jitter modulator circuit includes models of N parallel connected transmission lines and modulating includes providing the first input signal, at each of a series of times t, to the N transmission line models and selecting an output of two of the N transmission line models based on the second input. The modulated signal is formed based on the selected outputs of the two N transmission lines models.

公开(公告)号：US20180349537A1

公开(公告)日：2018-12-06

申请号：US15806397

申请日：2017-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhaoqing Chen

IPC: G06F17/50

Abstract: Embodiments of the present invention are directed to a computer-implemented method of simulating forward traveling voltages in a simulated circuit. The method includes inserting a traveling wave probe, via a processor, at an observation point of a simulated transmission line. The processor applies a first signal at an input of the traveling wave probe, and evaluates an output of the traveling wave probe. The processor next determines an instantaneous wave forward voltage and an instantaneous wave backward voltage at the traveling wave probe, and displays the instantaneous wave forward voltage and the instantaneous wave backward voltage via an output device.

公开(公告)号：US20170242947A1

公开(公告)日：2017-08-24

申请号：US15047152

申请日：2016-02-18

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78 ,  G06F2217/84

Abstract: A method of analyzing a transient response of an electronic circuit is includes: forming a model of a retimer that includes a data clocked latch; providing a latch input signal at the input of the model; forming an output signal based on the latch input signal with the voltage controlled voltage source, wherein the voltage controlled voltage source provides a high output when the latch input signal passes through a low to high transition value and continues to provide the high output until the latch input signal passes through a high to low transition value.

公开(公告)号：US20170091364A1

公开(公告)日：2017-03-30

申请号：US15367290

申请日：2016-12-02

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/36

Abstract: A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.

公开(公告)号：US09543241B2

公开(公告)日：2017-01-10

申请号：US14551185

申请日：2014-11-24

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: H01L23/498 ,  H01L23/528 ,  H04B3/32 ,  H01P3/02 ,  H01P3/08 ,  H05K1/02 ,  H04B1/00

CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。

公开(公告)号：US10803220B2

公开(公告)日：2020-10-13

申请号：US15613448

申请日：2017-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhaoqing Chen

IPC: G06F30/367 ,  G06F111/10

Abstract: Embodiments of the present invention are directed to a computer-implemented method of simulating forward traveling voltages in a simulated circuit. The method includes inserting a traveling wave probe, via a processor, at an observation point of a simulated transmission line. The processor applies a first signal at an input of the traveling wave probe, and evaluates an output of the traveling wave probe. The processor next determines an instantaneous wave forward voltage and an instantaneous wave backward voltage at the traveling wave probe, and displays the instantaneous wave forward voltage and the instantaneous wave backward voltage via an output device.

公开(公告)号：US09858370B2

公开(公告)日：2018-01-02

申请号：US14864953

申请日：2015-09-25

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/36

Abstract: A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.

公开(公告)号：US20170244504A1

公开(公告)日：2017-08-24

申请号：US15047011

申请日：2016-02-18

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: H04B17/391 ,  H04B3/46 ,  H04L27/00

CPC classification number: H04B3/46

Abstract: A method of analyzing a transient response of an electronic circuit includes receiving at a jitter modulator circuit first and second input signals, modulating the second input signal on the first input signal in the jitter modulator circuit and outputting a modulated signal based on the first and second input signals. The jitter modulator circuit includes models of N parallel connected transmission lines and modulating includes providing the first input signal, at each of a series of times t, to the N transmission line models and selecting an output of two of the N transmission line models based on the second input. The modulated signal is formed based on the selected outputs of the two N transmission lines models.

公开(公告)号：US09600619B2

公开(公告)日：2017-03-21

申请号：US14834767

申请日：2015-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: G06F17/50 ,  H05K3/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K1/0265 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0979

Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

公开(公告)号：US20160342724A1

公开(公告)日：2016-11-24

申请号：US14834767

申请日：2015-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: G06F17/50 ,  H05K3/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K1/0265 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0979

Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

Abstract translation: 一个方面是一种方法，其包括通过在电路设计系统的处理器上执行的电力通过放置工具来识别基于设计文件的多层电路板的电压域的源极和接收器，该设计文件定义了 多层电路板。 确定支持从源到汇的最大电流需求的多个电源通孔。 在多层电路板的位置处确定多个电源通孔的位置，该位置通过源极和漏极之间的电力通孔形成通路，并具有基本上相等的总路径长度，通过在源极和漏极之间限定的每个总路径 通过至少一个电源通孔。 设计文件被修改为在位置包括电源通孔。