公开(公告)号：US11567892B2

公开(公告)日：2023-01-31

申请号：US17230526

申请日：2021-04-14

Applicant: Infineon Technologies AG

Inventor： Tobias Islinger ,  Magnus-Maria Hell ,  Maximilian Mangst ,  Eric Pihet ,  Jens Repp

IPC: G06F13/42 ,  G06F13/38 ,  G06F1/3234 ,  G06F13/40 ,  G06F13/30

Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

公开(公告)号：US20180341615A1

公开(公告)日：2018-11-29

申请号：US16052371

申请日：2018-08-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Hinderer ,  David Astrom ,  Eric Pihet

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F13/4072 ,  G06F1/266 ,  G06F1/3296 ,  G06F13/4086 ,  G06F13/4282

Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

公开(公告)号：US20170286347A1

公开(公告)日：2017-10-05

申请号：US15091337

申请日：2016-04-05

Applicant: Infineon Technologies AG

Inventor： Thorsten Hinderer ,  David Astrom ,  Eric Pihet

IPC: G06F13/40 ,  G06F1/32 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/4072 ,  G06F1/266 ,  G06F1/3296 ,  G06F13/4086 ,  G06F13/4282

Abstract: Systems, devices, methods, and techniques are disclosed for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

公开(公告)号：US12009943B2

公开(公告)日：2024-06-11

申请号：US17468327

申请日：2021-09-07

Applicant: Infineon Technologies AG

Inventor： Jens Repp ,  Thorsten Hinderer ,  Maximilian Mangst ,  Eric Pihet

IPC: H04L12/40 ,  H03K5/01 ,  H03K17/687 ,  H03K5/00

CPC classification number: H04L12/40006 ,  H03K5/01 ,  H03K17/6872 ,  H03K2005/00013 ,  H04L2012/40215

Abstract: A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.

公开(公告)号：US20210334232A1

公开(公告)日：2021-10-28

申请号：US17230526

申请日：2021-04-14

Applicant: Infineon Technologies AG

Inventor： Tobias Islinger ,  Magnus-Maria Hell ,  Maximilian Mangst ,  Eric Pihet ,  Jens Repp

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/30 ,  G06F13/40 ,  G06F1/3234

Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

公开(公告)号：US20190334720A1

公开(公告)日：2019-10-31

申请号：US16395783

申请日：2019-04-26

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Vivin Richards Allimuthu Elavarasu ,  Eric Pihet

IPC: H04L9/32 ,  H04W12/02 ,  H04W12/10

Abstract: A transceiver is disclosed including a transmitter designed to output a first signal according to a physical communication protocol, and to output a second signal comprising at least one cryptographic datum. The first and the second signal may be overlaid onto one another as an overlay signal at the output of the transceiver, and may comply with the physical communication protocol. The overlay signal may be received and processed by a receiver.

公开(公告)号：US10120434B2

公开(公告)日：2018-11-06

申请号：US15154455

申请日：2016-05-13

Applicant: Infineon Technologies AG

Inventor： Eric Pihet

IPC: G06F3/00 ,  G06F1/32 ,  H03K3/356 ,  G06F13/40 ,  G06F13/42

Abstract: A semiconductor device is described herein. In accordance with one exemplary embodiment the semiconductor device includes a chip package, which includes at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin. The semiconductor device further includes a first circuit integrated in the semiconductor chip, wherein the first circuit is coupled to the first supply pin and to the ground pin, and a second circuit integrated in the semiconductor chip, wherein the second circuit is coupled to the first supply pin and to a virtual ground node. An electronic switch is configured to connect the virtual ground node with the first input pin dependent on the level of a first input signal.

公开(公告)号：US20170329388A1

公开(公告)日：2017-11-16

申请号：US15154455

申请日：2016-05-13

Applicant: Infineon Technologies AG

Inventor： Eric Pihet

IPC: G06F1/32 ,  G06F13/40 ,  G06F13/42 ,  H03K3/356

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F13/4022 ,  G06F13/4286 ,  H03K3/356 ,  H03K19/01759 ,  H03K19/018592

Abstract: A semiconductor device is described herein. In accordance with one exemplary embodiment the semiconductor device includes a chip package, which includes at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin. The semiconductor device further includes a first circuit integrated in the semiconductor chip, wherein the first circuit is coupled to the first supply pin and to the ground pin, and a second circuit integrated in the semiconductor chip, wherein the second circuit is coupled to the first supply pin and to a virtual ground node. An electronic switch is configured to connect the virtual ground node with the first input pin dependent on the level of a first input signal.