公开(公告)号：US20180269304A1

公开(公告)日：2018-09-20

申请号：US15986301

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Markus Bina ,  Hans-Joachim Schulze ,  Oana Julia Spulber

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.

公开(公告)号：US20170309619A1

公开(公告)日：2017-10-26

申请号：US15492279

申请日：2017-04-20

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Franz-Josef Niedernostheide ,  Alexander Philippou

IPC: H01L27/082 ,  H01L27/02 ,  H01L29/10 ,  H03K17/567

CPC classification number: H01L27/082 ,  H01L25/16 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/78 ,  H03K17/164 ,  H03K17/302 ,  H03K17/567

Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

公开(公告)号：US20170170823A1

公开(公告)日：2017-06-15

申请号：US15377750

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Jens Barrenscheen ,  Anton Mauder

IPC: H03K17/56 ,  H01L49/02 ,  G01R19/00 ,  H01L29/68

CPC classification number: H03K17/56 ,  G01R19/0092 ,  H01L28/60 ,  H01L29/68 ,  H01L29/7393 ,  H03K2217/0027

Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.

公开(公告)号：US11075290B2

公开(公告)日：2021-07-27

申请号：US16409454

申请日：2019-05-10

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH & Co. KG

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/00 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.

公开(公告)号：US10468148B2

公开(公告)日：2019-11-05

申请号：US15494599

申请日：2017-04-24

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: G21G1/06 ,  C30B31/20 ,  H01L21/261 ,  G21G4/02

Abstract: In various embodiments, a method of processing one or more semiconductor wafers is provided. The method includes positioning the one or more semiconductor wafers in an irradiation chamber, generating a neutron flux in a spallation chamber coupled to the irradiation chamber, moderating the neutron flux to produce a thermal neutron flux, and exposing the one or more semiconductor wafers to the thermal neutron flux to thereby induce the creation of dopant atoms in the one or more semiconductor wafers.

公开(公告)号：US10332973B2

公开(公告)日：2019-06-25

申请号：US15986301

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Markus Bina ,  Hans-Joachim Schulze ,  Oana Julia Spulber

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/36 ,  H01L29/08

Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.

公开(公告)号：US20190123186A1

公开(公告)日：2019-04-25

申请号：US16168136

申请日：2018-10-23

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Markus Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei ,  Caspar Leendertz ,  Christian Philipp Sandow

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08

Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.

公开(公告)号：US20180342605A1

公开(公告)日：2018-11-29

申请号：US15989778

申请日：2018-05-25

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348

Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.