公开(公告)号：US11594621B2

公开(公告)日：2023-02-28

申请号：US17087678

申请日：2020-11-03

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

公开(公告)号：US20210083081A1

公开(公告)日：2021-03-18

申请号：US17016498

申请日：2020-09-10

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Frank Dieter Pfirsch ,  Alexander Philippou ,  Christian Philipp Sandow

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: An RC IGBT with an n-barrier region in a transition section between a diode section and an IGBT section is presented.

公开(公告)号：US10347754B2

公开(公告)日：2019-07-09

申请号：US15704269

申请日：2017-09-14

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Christian Jaeger ,  Johannes Georg Laven ,  Max Christian Seifert ,  Antonio Vellei

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/66 ,  H01L29/739 ,  H01L29/866

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.

公开(公告)号：US10109624B2

公开(公告)日：2018-10-23

申请号：US15492279

申请日：2017-04-20

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Franz-Josef Niedernostheide ,  Alexander Philippou

IPC: H01L27/092 ,  G11C11/412 ,  H03K19/094 ,  H01L27/02 ,  G11C11/40 ,  G02F1/1362 ,  H01L21/306 ,  H01L27/082 ,  H03K17/567

Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

公开(公告)号：US10096531B2

公开(公告)日：2018-10-09

申请号：US14861569

申请日：2015-09-22

Applicant: Infineon Technologies AG

Inventor： Christian Jaeger ,  Johannes Georg Laven ,  Frank Dieter Pfirsch ,  Alexander Philippou

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40

Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode.

公开(公告)号：US20180053822A1

公开(公告)日：2018-02-22

申请号：US15675913

申请日：2017-08-14

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Anton Mauder

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/02 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0649 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/31144 ,  H01L27/0629 ,  H01L27/1207 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

公开(公告)号：US20150221756A1

公开(公告)日：2015-08-06

申请号：US14169712

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Johannes Georg Laven ,  Roman Baburske ,  Alexander Philippou

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0623 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.

Abstract translation: 半导体器件包括形成在从第一表面延伸到半导体本体的单元沟道结构之间的半导体台面。 半导体台面包括形成第一pn结的主体区域，其中在主体区域和与第一表面相对的第二表面之间具有漂移区域。 源区沿着半导体台面的纵向轴线彼此间隔开第一距离，并与身体区形成第二pn结。 具有源区的导电类型的屏障结构至少与漂移区形成单极同态结合，并且至少在与源区的垂直投影垂直于第一表面的垂直突起的外侧与体区相连。 在源区的垂直投影中可能不存在阻挡结构。

公开(公告)号：US20150076554A1

公开(公告)日：2015-03-19

申请号：US14026383

申请日：2013-09-13

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Alexander Philippou ,  Hans-Joachim Schulze ,  Christian Jaeger ,  Roman Baburske ,  Antonio Vellei

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66348 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

Abstract: An IGBT includes a mesa section that extends between two cell trench structures from a first surface of a semiconductor portion to a layer section of the semiconductor portion. A source region, which is electrically connected to an emitter electrode, is formed in the mesa section. A doped region, which is separated from the source region by a body region of a complementary conductivity type, includes a first portion with a first mean net impurity concentration and a second portion with a second mean net impurity concentration exceeding at least ten times the first mean net impurity concentration. In the mesa section the first portion extends from the body region to the layer section. The second portions of the doped region virtually narrow the mesa sections in a normal on-state of the IGBT.

Abstract translation: IGBT包括从半导体部分的第一表面到半导体部分的层部分的两个电池沟槽结构之间延伸的台面部分。 在台面部分形成有与发射电极电连接的源极区域。 通过互补导电类型的体区与源极区分离的掺杂区包括具有第一平均净杂质浓度的第一部分和具有超过第一平均净杂质浓度的至少十倍的第二平均净杂质浓度的第二部分 平均净杂质浓度。 在台面部分中，第一部分从身体区域延伸到层部分。 掺杂区域的第二部分在IGBT的正常导通状态下实际上使台面部分变窄。

公开(公告)号：US20240304709A1

公开(公告)日：2024-09-12

申请号：US18583993

申请日：2024-02-22

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Roman Baburske ,  Frank Pfirsch ,  Franz Josef Niedernostheide

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/06 ,  H01L29/43 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L27/0207 ,  H01L29/0603 ,  H01L29/435 ,  H01L29/66333

Abstract: A semiconductor device includes a semiconductor body having a trench transistor cell array. The trench transistor cell array includes a first trench transistor cell unit and a second trench transistor cell unit. Transistor cells based on the first trench transistor cell unit and transistor cells based on the second trench transistor cell unit are electrically connected in parallel. The first trench transistor cell unit has a first threshold voltage. The second trench transistor cell unit has a second threshold voltage larger than the first threshold voltage. An absolute value of dU/dt at turning on a nominal current of the transistor cell array is at least 50% of an absolute value of dU/dt at turning on 10% of the nominal current of the transistor cell array, dU/dt being the temporal derivate of a voltage U between load terminals of the trench transistor cell array.

公开(公告)号：US11075290B2

公开(公告)日：2021-07-27

申请号：US16409454

申请日：2019-05-10

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH & Co. KG

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/00 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.