公开(公告)号：US20180151673A1

公开(公告)日：2018-05-31

申请号：US15878317

申请日：2018-01-23

Applicant: Quantum Semiconductor LLC

Inventor： Carlos Jorge R.P. Augusto

IPC: H01L29/15 ,  H01L27/12 ,  H01L29/165 ,  H01L29/04

CPC classification number: H01L29/155 ,  H01L27/1203 ,  H01L27/146 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1462 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/151 ,  H01L29/161 ,  H01L29/165 ,  H01L29/68 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7833 ,  H01L31/035236 ,  H01L31/101 ,  H01L31/1812 ,  Y02E10/50

Abstract: A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

公开(公告)号：US09917155B2

公开(公告)日：2018-03-13

申请号：US15472229

申请日：2017-03-28

Applicant: Quantum Semiconductor LLC

Inventor： Carlos Jorge R. P. Augusto

IPC: H01L29/06 ,  H01L31/0328 ,  H01L21/00 ,  H01L29/15 ,  H01L29/165 ,  H01L29/04 ,  H01L27/12

CPC classification number: H01L29/155 ,  H01L27/1203 ,  H01L27/146 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1462 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/151 ,  H01L29/161 ,  H01L29/165 ,  H01L29/68 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7833 ,  H01L31/035236 ,  H01L31/101 ,  H01L31/1812 ,  Y02E10/50

Abstract: A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

公开(公告)号：US20170117147A1

公开(公告)日：2017-04-27

申请号：US15317997

申请日：2015-06-11

Applicant: President and Fellows of Harvard College

Inventor： Charles M. Lieber ,  Max Nathan Mankin ,  Robert Day ,  Ruixuan Gao

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/04 ,  H01L21/311

CPC classification number: H01L21/02433 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02238 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02557 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/31116 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/22 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/68 ,  H01L29/775 ,  Y10S977/762 ,  Y10S977/891 ,  Y10S977/932

Abstract: The present invention generally relates to nanoscale wires, and to systems and methods of producing nanoscale wires. In some aspects, the present invention is generally related to facet-specific deposition on semiconductor surfaces. In one embodiment, a first surface of a nanoscale wire, or a semiconductor, is preferentially oxidized relative to a second surface, and material is preferentially deposited on the second surface relative to the first surface. For example, the nanoscale wire or semiconductor may be a silicon nanowire that is initially exposed to an etchant to remove silicon oxide, then exposed to an oxidant under conditions such that one facet or surface (e.g., a {113} facet) is oxidized more quickly than another facet or surface (e.g., a {111} facet). Material may then be deposited or immobilized on the less-oxidized facet relative to the more-oxidized facet. Other embodiments of the invention may be directed to articles made thereby, devices containing such nanoscale wires or semiconductors, kits involving such nanoscale wires or semiconductors, semiconductor surfaces, or the like.

公开(公告)号：US09502404B2

公开(公告)日：2016-11-22

申请号：US14549316

申请日：2014-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Meng-Yueh Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/68 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L27/088 ,  H01L21/02518 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/68 ,  H01L29/7835 ,  H01L29/7848

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Abstract translation: 用于形成所描述的场效应晶体管（FET）的源极/漏极（S / D）区域的机构的实施例使得能够在用于循环沉积/蚀刻的蚀刻工艺的蚀刻气体混合物中形成外延生长的含硅材料，而不使用GeH 4 （CDE）过程。 蚀刻工艺在不同于沉积工艺的温度下进行，以使蚀刻气体更有效率。 结果，蚀刻时间减少并且生产量增加。

公开(公告)号：US09024367B2

公开(公告)日：2015-05-05

申请号：US13773985

申请日：2013-02-22

Applicant: The Regents of the University of California

Inventor： William Regan ,  Alexander Zettl

IPC: H01L29/68 ,  H01L31/07 ,  H01L29/66 ,  H01L31/06

CPC classification number: H01L29/68 ,  H01L29/66356 ,  H01L31/06 ,  H01L31/062 ,  H01L31/07 ,  Y02E10/50

Abstract: This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate.

Abstract translation: 本公开提供了与场效应p-n结相关的系统，方法和装置。 在一个方面，一种器件包括欧姆接触，设置在欧姆接触上的半导体层，设置在半导体层上的至少一个整流触点，包括设置在至少一个整流触点和半导体层上的层的栅极和 栅极触点设置在层上。 整流触点的横向宽度小于半导体层的半导体耗尽宽度。 栅极触点电连接到欧姆接触，以产生自门控反馈回路，其被配置为保持栅极的栅极电场。

公开(公告)号：US08957463B2

公开(公告)日：2015-02-17

申请号：US13597610

申请日：2012-08-29

Applicant: Ali Afzali-Ardakani ,  Damon Farmer

Inventor： Ali Afzali-Ardakani ,  Damon Farmer

IPC: H01L29/78

CPC classification number: H01L29/88 ,  H01L29/0895 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66037 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/66977 ,  H01L29/68 ,  H01L29/7311

Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.

Abstract translation: 提供了一个门极可调二极管。 栅极可调二极管包括形成在栅电极上的栅极电介质和形成在栅极电介质上的石墨烯电极。 此外，栅极可调二极管包括形成在石墨烯电极上的隧道电介质和形成在隧道电介质上的隧道电极。

公开(公告)号：US4558431A

公开(公告)日：1985-12-10

申请号：US560308

申请日：1983-12-12

Applicant: Noboru Satoh

Inventor： Noboru Satoh

IPC: H01L21/8249 ,  G11C27/00 ,  G11C27/02 ,  H01L21/331 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L29/68 ,  H01L29/73 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: H01L29/68 ,  G11C27/005 ,  G11C27/02

Abstract: The non-volatile semiconductor memory elements having an MIS structure show a hysteresis curve in the gate voltage-the threshold voltage characteristic. The continuously changing region of the hysteresis curve is used to operate the memory elements as analog memories. The input analog signal is applied to the gate electrode of a selected memory element after it is converted to have a voltage within the continuously changing region, to change the threshold voltage of the selected memory element. The changed threshold voltage is read out in read-out operation.

Abstract translation: 具有MIS结构的非易失性半导体存储元件示出了栅极电压（阈值电压特性）中的滞后曲线。 滞后曲线的连续变化区域用于作为模拟存储器来操作存储元件。 输入模拟信号在被转换成具有连续变化区域内的电压的情况下被施加到所选存储元件的栅电极，以改变所选存储元件的阈值电压。 在读出操作中读出改变的阈值电压。

公开(公告)号：US3331998A

公开(公告)日：1967-07-18

申请号：US44715765

申请日：1965-04-12

Applicant: HUGHES AIRCRAFT CO

Inventor： RAINER ZULEEG

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/68 ,  H01L29/86

CPC classification number: H01L29/68 ,  H01L21/00 ,  H01L27/00 ,  H01L29/86

公开(公告)号：US3225272A

公开(公告)日：1965-12-21

申请号：US8426961

申请日：1961-01-23

Applicant: BENDIX CORP

Inventor： CRONEMEYER DONALD C

IPC: H01L21/24 ,  H01L27/00 ,  H01L29/68 ,  H01L29/73

CPC classification number: H01L29/68 ,  H01L21/24 ,  H01L27/00 ,  H01L29/73

公开(公告)号：US20180204934A1

公开(公告)日：2018-07-19

申请号：US15809292

申请日：2017-11-10

Applicant: Skyworks Solutions, Inc.

Inventor： Cristian Cismaru ,  Peter J. Zampardi, Jr.

IPC: H01L29/68 ,  H01L29/872 ,  H01L29/47 ,  H01L29/66 ,  H01L29/73 ,  H01L31/02 ,  H01L29/06

CPC classification number: H01L29/68 ,  H01L29/0692 ,  H01L29/475 ,  H01L29/66007 ,  H01L29/66212 ,  H01L29/66318 ,  H01L29/73 ,  H01L29/872 ,  H01L31/02002 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15184 ,  H01L2924/00014

Abstract: Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.