公开(公告)号：US20150032914A1

公开(公告)日：2015-01-29

申请号：US13951518

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Simon Cottam

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G01R31/31937 ,  G06F13/18 ,  G06F13/287 ,  G06F13/4269

Abstract: A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.

Abstract translation: 一种用于经由多个直接存储器访问（DMA）事务在存储器和外围单元之间传送数据的系统和方法，其中相应的时间戳被分配和/或附加到所述多个DMA事务中的至少两个。

公开(公告)号：US20140258684A1

公开(公告)日：2014-09-11

申请号：US13786550

申请日：2013-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Neil Hastie ,  Simon Brewerton

IPC: G06F9/30

CPC classification number: G06F9/3005 ,  G06F11/0724 ,  G06F11/0793 ,  G06F11/1641

Abstract: A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.

Abstract translation: 用于增加锁步核心可用性的系统和方法提供将主CPU内核的状态写入状态缓冲器，由主CPU内核执行任务的一个或多个指令以为每个执行的指令生成第一输出，并且执行 一个或多个任务的指令由检验CPU核心产生用于每个执行的指令的第二输出。 该方法还包括将第一输出与第二输出进行比较，如果第一输出与第二输出不匹配，则产生一个或多个控制信号，并且基于一个或多个控制信号的产生， 主CPU内核从状态缓冲区到主CPU内核和核心CPU核心。

公开(公告)号：US20140108869A1

公开(公告)日：2014-04-17

申请号：US13651775

申请日：2012-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Simon Brewerton ,  Simon Cottam ,  Frank Hellwig

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括一组事务控制寄存器，用于接收共同描述要由DMA控制器处理的数据传输的事务控制集合的序列。 总线控制器读取和写入存储器，而DMA控制器执行第一事务控制集以完成事务控制集序列中描述的部分数据传输。 完整性检查器基于在执行第一事务控制集期间由DMA控制器实际处理的数据或地址来确定实际的错误检测码。 完整性检查器还基于实际错误检测码是否与包含在事务控制集合的顺序的第二事务控制集中的期望错误检测码相同来选择性地标记错误。

公开(公告)号：US20140019805A1

公开(公告)日：2014-01-16

申请号：US14027464

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Barnardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

IPC: G06F11/263

CPC classification number: G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract translation: 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。