公开(公告)号：US11935875B2

公开(公告)日：2024-03-19

申请号：US17537678

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Waldemar Jakobi ,  Michael Niendorf

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement includes a power electronics substrate comprising a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad, first and second transistor dies mounted on the first load pad, third and fourth transistor dies mounted the first DC voltage pad, the first and second transistor dies collectively form a first switch, the third and fourth transistor dies collectively form a second switch, the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies, and an impedance of a first load connection to the third transistor die is greater than an impedance of a second load connection to the fourth transistor die.

公开(公告)号：US20240079297A1

公开(公告)日：2024-03-07

申请号：US17903512

申请日：2022-09-06

Applicant: Infineon Technologies AG

Inventor： Peter Luniewski ,  Markus Neubert ,  Michael Fuegl ,  Waldemar Jakobi ,  Michael Leipenat ,  Egbert Lamminger

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49562 ,  H01L24/48 ,  H01L2224/48245

Abstract: A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

公开(公告)号：US20230361087A1

公开(公告)日：2023-11-09

申请号：US17736519

申请日：2022-05-04

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Baessler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L25/072 ,  H01L23/49811 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49833 ,  H01L23/4952 ,  H01L23/3121

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

公开(公告)号：US20230170333A1

公开(公告)日：2023-06-01

申请号：US17537678

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Waldemar Jakobi ,  Michael Niendorf

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/072 ,  H01L24/48 ,  H01L23/49811 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement includes a power electronics substrate comprising a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad, first and second transistor dies mounted on the first load pad, third and fourth transistor dies mounted the first DC voltage pad, the first and second transistor dies collectively form a first switch, the third and fourth transistor dies collectively form a second switch, the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies, and an impedance of a first load connection to the third transistor die is greater than an impedance of a second load connection to the fourth transistor die.

公开(公告)号：US20190139880A1

公开(公告)日：2019-05-09

申请号：US16179015

申请日：2018-11-02

Applicant: Infineon Technologies AG

Inventor： Waldemar Jakobi ,  Christoph Koch

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L23/538

Abstract: A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base section and first, second and third sections, the third section arranged between the first and second sections. The second conductor track has first and second sections. The first section of the second conductor track is arranged between the first and third sections of the first conductor track. The second section of the second conductor track is arranged between the second and third sections of the first conductor track. The third section of the first conductor track is arranged between the first and second sections of the second conductor track. First and second subsets of semiconductor chips are arranged on the first section of the second conductor track. Third and fourth subsets of semiconductor chips are arranged on the second section of the second conductor track.