公开(公告)号：US11682611B2

公开(公告)日：2023-06-20

申请号：US16907734

申请日：2020-06-22

Applicant: Infineon Technologies AG

Inventor： Michael Niendorf ,  Ludwig Busch ,  Oliver Markus Kreiter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/4952 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2924/1203 ,  H01L2924/13055

Abstract: A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

公开(公告)号：US20240266300A1

公开(公告)日：2024-08-08

申请号：US18107257

申请日：2023-02-08

Applicant: Infineon Technologies AG

Inventor： Marco Bäßler ,  Michael Niendorf

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/49861 ,  H05K1/18 ,  H01L23/3121 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/48137 ,  H01L2224/48175 ,  H05K2201/09063 ,  H05K2201/09409 ,  H05K2201/1059

Abstract: A power semiconductor module includes: an electrically insulative enclosure; a plurality of power semiconductor dies attached to a substrate inside the electrically insulative enclosure; a lead frame or clip frame disposed above the power semiconductor dies inside the electrically insulative enclosure and electrically connected to the power semiconductor dies; a plurality of contact pins attached to the lead frame or clip frame and protruding through a first side of the electrically insulative enclosure to form an electrical connection interface outside the electrically insulative enclosure; and a plurality of vibration dampeners attached to the lead frame or clip frame. The vibration dampeners protrude through the first side of the electrically insulative enclosure and are separate from the electrical connection interface. The vibration dampeners are configured to dampen vibrations at a circuit board designed to be mounted to the module and do not affect electrical operation of the power semiconductor module.

公开(公告)号：US20220262693A1

公开(公告)日：2022-08-18

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US20210398887A1

公开(公告)日：2021-12-23

申请号：US16907734

申请日：2020-06-22

Applicant: Infineon Technologies AG

Inventor： Michael Niendorf ,  Ludwig Busch ,  Oliver Markus Kreiter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00

Abstract: A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

公开(公告)号：US11935875B2

公开(公告)日：2024-03-19

申请号：US17537678

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Waldemar Jakobi ,  Michael Niendorf

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement includes a power electronics substrate comprising a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad, first and second transistor dies mounted on the first load pad, third and fourth transistor dies mounted the first DC voltage pad, the first and second transistor dies collectively form a first switch, the third and fourth transistor dies collectively form a second switch, the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies, and an impedance of a first load connection to the third transistor die is greater than an impedance of a second load connection to the fourth transistor die.

公开(公告)号：US20230170333A1

公开(公告)日：2023-06-01

申请号：US17537678

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Waldemar Jakobi ,  Michael Niendorf

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/072 ,  H01L24/48 ,  H01L23/49811 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement includes a power electronics substrate comprising a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad, first and second transistor dies mounted on the first load pad, third and fourth transistor dies mounted the first DC voltage pad, the first and second transistor dies collectively form a first switch, the third and fourth transistor dies collectively form a second switch, the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies, and an impedance of a first load connection to the third transistor die is greater than an impedance of a second load connection to the fourth transistor die.

公开(公告)号：US11621204B2

公开(公告)日：2023-04-04

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.