公开(公告)号：US10593709B2

公开(公告)日：2020-03-17

申请号：US16130450

申请日：2018-09-13

Applicant: InnoLux Corporation

Inventor： Hsin-Hung Lin ,  Chin-Chi Chen

IPC: H01L27/12 ,  H01L27/02 ,  H01L29/786 ,  H01L27/146 ,  H01L23/60 ,  G02F1/1362

Abstract: A panel device includes a substrate, a common electrode, and an electrostatic protection component. The substrate includes an active area and a peripheral area, the peripheral area is outside of the active area, and a plurality of signal lines is disposed on the substrate. The common electrode is disposed on the substrate, and at least part of the common electrode is disposed in the peripheral area. The electrostatic protection component is disposed in the peripheral area of the substrate and electrically connected to one of the plurality of signal lines and the common electrode, and the electrostatic protection component includes a first double-gate transistor. The first double-gate transistor includes a first gate, a second gate, a first electrode and a second electrode. The first gate is electrically connected to the first electrode, and the second gate is electrically connected to the second electrode.

公开(公告)号：US09076872B2

公开(公告)日：2015-07-07

申请号：US14478124

申请日：2014-09-05

Applicant: InnoLux Corporation

Inventor： Hsin-Hung Lin ,  Jung-Fang Chang ,  Ker-Yih Kao

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L23/31 ,  H01L23/48 ,  H01L29/417 ,  H01L29/51 ,  H01L21/441 ,  H01L21/47 ,  H01L21/471 ,  H01L21/4757

CPC classification number: H01L27/1225 ,  H01L21/441 ,  H01L21/47 ,  H01L21/471 ,  H01L21/47573 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract translation: 公开了一种在基板上包括栅电极的薄膜晶体管。 栅极电介质层设置在栅电极和衬底上，源极/漏电极设置在覆盖栅电极的两个边缘部分的栅极电介质层上。 沟道层设置在覆盖栅极电极的中心部分的栅极电介质层上，沟道区域与源极/漏极接触。 绝缘覆盖层覆盖在沟道层上，其中沟道层包括氧化物半导体。

公开(公告)号：US10304965B2

公开(公告)日：2019-05-28

申请号：US15436752

申请日：2017-02-17

Applicant: Innolux Corporation

Inventor： Chao-Hsiang Wang ,  Yi-Ching Chen ,  Kuan-Feng Lee ,  Hsin-Hung Lin ,  Shou-Pu Yeh ,  Yuan-Lin Wu

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32

Abstract: A display panel includes a first substrate, and the first substrate includes a base plate; a first conductive line disposed on the base plate and extending along the first direction; a second conductive line and a third conductive line disposed on the base plate and extending along the second direction; a contact pad positioned between the second and third conductive lines; a semi-conductive layer connecting the contact pad and the second conductive line, and the semi-conductive layer having a thickness d; and a pixel electrode connecting the contact pad. The semi-conductive layer has a channel width W (μm) and a channel length L (μm) between the contact pad and the second conductive line, and a pixel distance Px (μm) between the second and third conductive lines along the first direction, wherein the channel width W is conformed to the following equation: ( 3.035 - 1.5 ) ≤ W - 0.008 × ( P x × L d ) ≤ ( 3.035 + 1.5 ) .

公开(公告)号：US09368631B2

公开(公告)日：2016-06-14

申请号：US14478148

申请日：2014-09-05

Applicant: InnoLux Corporation

Inventor： Hsin-Hung Lin ,  Jung-Fang Chang ,  Ker-Yih Kao

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L23/31 ,  H01L23/48 ,  H01L29/417 ,  H01L29/51 ,  H01L21/441 ,  H01L21/47 ,  H01L21/471 ,  H01L21/4757

CPC classification number: H01L27/1225 ,  H01L21/441 ,  H01L21/47 ,  H01L21/471 ,  H01L21/47573 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

公开(公告)号：US09362408B2

公开(公告)日：2016-06-07

申请号：US14478172

申请日：2014-09-05

Applicant: InnoLux Corporation

Inventor： Hsin-Hung Lin ,  Jung-Fang Chang ,  Ker-Yih Kao

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L23/31 ,  H01L23/48 ,  H01L29/417 ,  H01L29/51 ,  H01L21/441 ,  H01L21/47 ,  H01L21/471 ,  H01L21/4757

CPC classification number: H01L27/1225 ,  H01L21/441 ,  H01L21/47 ,  H01L21/471 ,  H01L21/47573 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

Abstract translation: 公开了一种在基板上包括栅电极的薄膜晶体管。 栅极电介质层设置在栅电极和衬底上，源极/漏电极设置在覆盖栅电极的两个边缘部分的栅极电介质层上。 沟道层设置在覆盖栅极电极的中心部分的栅极电介质层上，沟道区域与源极/漏极接触。 绝缘覆盖层覆盖在沟道层上，其中沟道层包括氧化物半导体。