公开(公告)号：US20150007196A1

公开(公告)日：2015-01-01

申请号：US13931657

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： BRET L. TOLL ,  Jason W. Brandt ,  Eliezer Weissmann ,  Inder M. Sodhi ,  David A. Koufaty ,  Scott D. Hanh

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5044 ,  G06F9/5088 ,  Y02D10/22 ,  Y02D10/32

Abstract: A processor of an aspect includes a first heterogeneous physical compute element having a first set of supported instructions and architectural features, and a second heterogeneous physical compute element having a second set of supported instructions and architectural features. The second set of supported instructions and architectural features is different than the first set of supported instructions and architectural features. The processor also includes a workload and architectural state migration module coupled with the first and second heterogeneous physical compute elements. The workload and state migration module is operable to migrate a workload and associated architectural state from the first heterogeneous physical compute element to the second heterogeneous physical compute element in response to an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature on the first heterogeneous physical compute element.

Abstract translation: 一方面的处理器包括具有第一组支持的指令和架构特征的第一异构物理计算元件，以及具有第二组支持的指令和架构特征的第二异构物理计算元件。 第二组支持的指令和架构特征与第一组支持的指令和架构特征不同。 处理器还包括与第一和第二异构物理计算元件耦合的工作负载和架构状态迁移模块。 工作负载和状态迁移模块可操作以响应于工作负载尝试执行不支持的指令和不支持的指令中的至少一个而将工作负载和相关联的架构状态从第一异构物理计算元件迁移到第二异构物理计算元件 第一个异构物理计算元素的架构特征。

公开(公告)号：US20230409732A1

公开(公告)日：2023-12-21

申请号：US18357066

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  BRET L. TOLL ,  MARK J. CHARNEY

IPC: G06F21/62 ,  G06F16/27 ,  G06F21/70 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F21/6227 ,  G06F16/27 ,  G06F21/6254 ,  G06F21/70 ,  G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30101 ,  G06F9/3802

Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.

公开(公告)号：US20200097290A1

公开(公告)日：2020-03-26

申请号：US16560223

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： JESUS CORBAL SAN ADRIAN ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY ,  MILIND B. GIRKAR ,  BRET L. TOLL ,  ROGER ESPASA ,  GUILLEM SOLE ,  JAIRO BALART ,  BRIAN HICKMANN

IPC: G06F9/30 ,  G06F15/80 ,  G06F16/901

Abstract: An apparatus and method for performing a vector permute. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element and to responsively copy the source data element to the corresponding destination data element in the destination vector register.

公开(公告)号：US20170357510A1

公开(公告)日：2017-12-14

申请号：US15668461

申请日：2017-08-03

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL SAN ADRIAN ,  BRET L. TOLL ,  MARK J. CHARNEY ,  ZEEV SPERBER ,  AMIT GRADSTEIN

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802 ,  G06F12/0615

Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20170242704A1

公开(公告)日：2017-08-24

申请号：US15452631

申请日：2017-03-07

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  BRET L. TOLL ,  MARK J. CHARNEY ,  ZEEV SPERBER ,  AMIT GRADSTEIN

IPC: G06F9/30

Abstract: An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second instructions select a first group of input vector elements from one of multiple first non-overlapping sections of respective first and second input vectors. Each of the multiple first non-overlapping sections have a same bit width as the first group. Both the third and fourth instructions select a second group of input vector elements from one of multiple second non-overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of multiple second non-overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups at a first granularity a second granularity.

公开(公告)号：US20170169246A1

公开(公告)日：2017-06-15

申请号：US15245113

申请日：2016-08-23

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  BRET L. TOLL ,  MARK J. CHARNEY

IPC: G06F21/62 ,  G06F9/38 ,  G06F17/30 ,  G06F9/30

CPC classification number: G06F21/6227 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3802 ,  G06F17/30575 ,  G06F21/6254 ,  G06F21/70

Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.

公开(公告)号：US20160188530A1

公开(公告)日：2016-06-30

申请号：US14583644

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： JESUS CORBAL SAN ADRIAN ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY ,  MILIND B. GIRKAR ,  BRET L. TOLL ,  ROGER ESPASA ,  GUILLEM SOLE ,  JAIRO BALART ,  BRIAN HICKMAN

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/764 ,  G06F9/30032 ,  G06F15/8053 ,  G06F15/8084 ,  G06F16/9017 ,  G06F2209/462

Abstract: An apparatus and method for performing a vector permute. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element and to responsively copy the source data element to the corresponding destination data element in the destination vector register.

Abstract translation: 用于执行向量置换的装置和方法。 例如，处理器的一个实施例包括：源向量寄存器，用于存储多个源数据元素; 目的地向量寄存器，用于存储多个目的地数据元素; 用于存储多个控制数据元素的控制向量寄存器，与目的地数据元素之一对应的每个控制数据元素，并且包括指示源数据元素是否被复制到对应的目的地数据元素的N位值; 向量置换逻辑，以将每个控制数据元素的N位值与立即数的N位部分进行比较，以确定是否将源数据元素复制到对应的目标数据元素，其中如果N位值匹配，则向量置换 逻辑是使用包括在控制数据元素中的索引值来识别源数据元素，并且将源数据元素响应地复制到目的地向量寄存器中的相应目的地数据元素。

公开(公告)号：US20150006858A1

公开(公告)日：2015-01-01

申请号：US13931739

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： BRET L. TOLL ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Nail

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30018 ,  G06F9/30036

Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

Abstract translation: 处理器包括处理器不使用打包数据操作屏蔽的第一模式，以及处理器将使用打包数据操作屏蔽的第二模式。 解码单元，用于对第一模式中的给定打包数据操作的未屏蔽打包数据指令进行解码，并且解码用于第二模式中给定打包数据操作的屏蔽版本的屏蔽打包数据指令。 指令具有相同的指令长度。 被屏蔽的指令具有指定掩码的位。 执行单元与解码单元耦合。 执行单元响应于解码单元对第一模式中的未屏蔽指令进行解码，以执行给定的打包数据操作。 执行单元响应于解码单元对第二模式中的屏蔽指令进行解码，以执行给定打包数据操作的屏蔽版本。