公开(公告)号：US11789892B2

公开(公告)日：2023-10-17

申请号：US17738625

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US11327920B2

公开(公告)日：2022-05-10

申请号：US16926524

申请日：2020-07-10

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/00 ,  G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US20200210366A1

公开(公告)日：2020-07-02

申请号：US16812156

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US09720439B2

公开(公告)日：2017-08-01

申请号：US14866866

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Bruce A. Tennant

IPC: G06F1/10 ,  G06F1/12

CPC classification number: G06F1/10 ,  G06F1/12

Abstract: Systems, methods, and apparatuses are described for deskewing between multiple lane groups of deskewed data streams. Multiple distinct and deskewed lane groups can be aligned by utilizing an inter-group synchronized set of counters. The counters supply a way to measure the time delta (counter difference) in clocks between the multiple streams. Using this delta, one or more streams can be stalled to align the multiple streams. The counter values are communicated between the multiple groups in a way that they align to set data stream markers. These fixed markers and the breaking up of the counters in relation to the periodicity of the markers allows for a robust way to compare the multiple streams and calculate an accurate time delta.

公开(公告)号：US20170090510A1

公开(公告)日：2017-03-30

申请号：US14866866

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Bruce A. Tennant

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/12

Abstract: Systems, methods, and apparatuses are described for deskewing between multiple lane groups of deskewed data streams. Multiple distinct and deskewed lane groups can be aligned by utilizing an inter-group synchronized set of counters. The counters supply a way to measure the time delta (counter difference) in clocks between the multiple streams. Using this delta, one or more streams can be stalled to align the multiple streams. The counter values are communicated between the multiple groups in a way that they align to set data stream markers. These fixed markers and the breaking up of the counters in relation to the periodicity of the markers allows for a robust way to compare the multiple streams and calculate an accurate time delta.

公开(公告)号：US09124455B1

公开(公告)日：2015-09-01

申请号：US14495768

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Su Wei Lim ,  Ronald W. Swartz ,  Yueming Jiang ,  Hooi Kar Loo ,  Athourina Gevergiz ,  Bruce A. Tennant ,  Yick Yaw Ho ,  Poh Thiam Teoh ,  Jennifer Chin ,  Hui Shi

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03343 ,  H04L2025/03681

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。 该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。 接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。