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公开(公告)号：US10038574B2
公开(公告)日：2018-07-31
申请号：US15463891
申请日：2017-03-20
Applicant: Intel Corporation
Inventor： Syed S. Islam , Yick Yaw Ho , Ronald W. Swartz
CPC classification number: H04L25/03057 , H04L25/0272 , H04L25/0296 , H04L25/03254 , H04L25/03885 , H04L25/06 , H04L25/10
Abstract: Described is an apparatus which comprises: a first capacitor coupled to a first input pad; a second capacitor coupled to second input pad; a first resistor coupled to the second capacitor; a third capacitor coupled in series with the first resistor; a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and a differential amplifier coupled to the first and second capacitors and to the first and second resistors.
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公开(公告)号：US09602315B2
公开(公告)日：2017-03-21
申请号：US14569574
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Syed S. Islam , Yick Yaw Ho , Ronald W. Swartz
CPC classification number: H04L25/03057 , H04L25/0272 , H04L25/0296 , H04L25/03254 , H04L25/03885 , H04L25/06 , H04L25/10
Abstract: Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.
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Patent Agency Ranking
公开(公告)号：US09124455B1
公开(公告)日：2015-09-01
申请号：US14495768
申请日：2014-09-24
Applicant: INTEL CORPORATION
Inventor： Su Wei Lim , Ronald W. Swartz , Yueming Jiang , Hooi Kar Loo , Athourina Gevergiz , Bruce A. Tennant , Yick Yaw Ho , Poh Thiam Teoh , Jennifer Chin , Hui Shi
CPC classification number: H04L25/03885 , H04L25/03343 , H04L2025/03681
Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.
Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。 该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。 接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。
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4.发明申请公开(公告)号：US20160173299A1
公开(公告)日：2016-06-16
申请号：US14569574
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Syed S. Islam , Yick Yaw Ho , Ronald W. Swartz
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/0272 , H04L25/0296 , H04L25/03254 , H04L25/03885 , H04L25/06 , H04L25/10
Abstract: Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.
Abstract translation: 描述了一种装置，包括：放大器; 以及与基线漂移（BLW）校正器集成的被动连续时间线性均衡器，其中集成均衡器和BLW校正器耦合到放大器。
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公开(公告)号：US09959222B2
公开(公告)日：2018-05-01
申请号：US14498474
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Huimin Chen , Keith A. Jones , John L. Baudrexl , Ronald W. Swartz , Vui Yong Liew
CPC classification number: G06F13/22 , G06F13/4054 , G06F13/4286
Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.
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公开(公告)号：US09910814B2
公开(公告)日：2018-03-06
申请号：US14658026
申请日：2015-03-13
Applicant: Intel Corporation
Inventor： Bryan L. Spry , Su Wei Lim , Mikal C. Hunsaker , Rohit R. Verma , Lily P. Looi , Ronald W. Swartz , Michael W. Leddige , Vui Yong Liew
CPC classification number: G06F13/4221 , G06F13/122 , G06F13/4022 , G06F13/4265 , Y02D10/14 , Y02D10/151
Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.
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公开(公告)号：US20160092381A1
公开(公告)日：2016-03-31
申请号：US14498474
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Huimin Chen , Keith A. Jones , John L. Baudrexl , Ronald W. Swartz , Vui Yong Liew
CPC classification number: G06F13/22 , G06F13/4054 , G06F13/4286
Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.
Abstract translation: 输入互连协议的第一状态。 根据协议将特定信号发送到通过链路的设备。 在第一状态期间，检测到在第一状态下接收到对特定信号的响应。 确定设备基于接收到的响应支持协议之外的配置模式。 基于响应输入配置模式。 在配置模式下发送一个或多个带内配置消息。
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