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    DUAL BUS STANDARD SWITCHING BUS CONTROLLER
    1.
    发明申请
    DUAL BUS STANDARD SWITCHING BUS CONTROLLER 审中-公开
    双总线标准开关总线控制器

    公开(公告)号：US20160085707A1

    公开(公告)日：2016-03-24

    申请号：US14801880

    申请日：2015-07-17

    Applicant: Intel Corporation

    Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

    Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

    Abstract translation: 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

    Innovative high speed serial controller testing
    2.
    发明授权
    Innovative high speed serial controller testing 有权

    公开(公告)号：US10657092B2

    公开(公告)日：2020-05-19

    申请号：US15199302

    申请日：2016-06-30

    Applicant: Intel Corporation

    Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Hem Doshi ,  Hooi Kar Loo ,  Suketu U. Bhatt

    IPC: G06F13/42

    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing. For instance, in accordance with one embodiment, there is a functional semiconductor device, comprising: a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a transaction and issue the transaction onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to modify the transaction received to form a modified transaction; in which the virtualized device logic is to issue the modified transaction onto the device fabric; and in which the modified transaction is returned to the transaction originator. Other related embodiments are disclosed.

    Dual bus standard switching bus controller
    3.
    发明授权
    Dual bus standard switching bus controller 有权
    双总线标准交换总线控制器

    公开(公告)号：US09098642B2

    公开(公告)日：2015-08-04

    申请号：US14194893

    申请日：2014-03-03

    Applicant: Intel Corporation

    Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

    IPC: G06F13/20 ,  G06F13/28 ,  G06F13/40 ,  G06F13/38

    CPC classification number: G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

    Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

    Abstract translation: 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

    Dual bus standard switching bus controller
    4.
    发明授权
    Dual bus standard switching bus controller 有权

    公开(公告)号：US10229080B2

    公开(公告)日：2019-03-12

    申请号：US14801880

    申请日：2015-07-17

    Applicant: Intel Corporation

    Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

    IPC: G06F13/20 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

    Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

    HARDWARE MECHANISMS FOR LINK ENCRYPTION
    6.
    发明申请
    HARDWARE MECHANISMS FOR LINK ENCRYPTION 审中-公开

    公开(公告)号：US20190229901A1

    公开(公告)日：2019-07-25

    申请号：US16368800

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Reouven Elbaz ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Su Wei Lim ,  Patrick D. Maloney ,  Santosh Ghosh

    IPC: H04L9/08 ,  H04L9/12 ,  G06F13/42

    Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

    Link equalization mechanism
    8.
    发明授权
    Link equalization mechanism 有权
    链路均衡机制

    公开(公告)号：US09124455B1

    公开(公告)日：2015-09-01

    申请号：US14495768

    申请日：2014-09-24

    Applicant: INTEL CORPORATION

    Inventor： Su Wei Lim ,  Ronald W. Swartz ,  Yueming Jiang ,  Hooi Kar Loo ,  Athourina Gevergiz ,  Bruce A. Tennant ,  Yick Yaw Ho ,  Poh Thiam Teoh ,  Jennifer Chin ,  Hui Shi

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03885 ,  H04L25/03343 ,  H04L2025/03681

    Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

    Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。 该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。 接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。

    Hardware mechanisms for link encryption
    9.
    发明授权
    Hardware mechanisms for link encryption 有权

    公开(公告)号：US11533170B2

    公开(公告)日：2022-12-20

    申请号：US16368800

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Reouven Elbaz ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Su Wei Lim ,  Patrick D. Maloney ,  Santosh Ghosh

    IPC: H04L9/08 ,  G06F13/42 ,  H04L9/06 ,  H04L9/12 ,  H04L9/14

    Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

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