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    Virtual storage services for client computing devices
    11.
    发明授权
    Virtual storage services for client computing devices 有权

    公开(公告)号：US11615194B2

    公开(公告)日：2023-03-28

    申请号：US16975661

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Changzheng Wei ,  Ziye Yang ,  Junyuan Wang ,  Cunming Liang ,  Junhua Hou ,  Weigang Li ,  Ping Yu ,  Yi Yang ,  Baoqian Li ,  Xin Zeng

    IPC: G06F21/60 ,  G06F16/14 ,  H04L9/08 ,  H04L9/40 ,  H04L67/1097

    Abstract: Embodiments include apparatuses, methods, and systems including one or more servers and one or more storage devices, coupled with each other, to provide virtual storage service to store a file and meta data of the file for a client computing device. The file and the meta data of the file may be encrypted by the client computing device before providing to the virtual storage service. The file may be encrypted with a secret key of the client computing device, and the meta data of the file may be encrypted with a shared session key between the client computing device and the virtual storage service. The encrypted file may be stored in the one or more storage devices, and the encrypted meta data of the file may be stored in one or more secured areas of the one or more servers. Other embodiments may also be described and claimed.

    Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration
    12.
    发明授权
    Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration 有权

    公开(公告)号：US11372684B2

    公开(公告)日：2022-06-28

    申请号：US17220763

    申请日：2021-04-01

    Applicant: Intel Corporation

    Inventor： Ned M. Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

    IPC: G06F9/50 ,  G06F21/76 ,  G06F21/60

    Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).

    RECONFIGURABLE DEVICE BITSTREAM KEY AUTHENTICATION
    16.
    发明申请
    RECONFIGURABLE DEVICE BITSTREAM KEY AUTHENTICATION 有权

    公开(公告)号：US20210012035A1

    公开(公告)日：2021-01-14

    申请号：US16614236

    申请日：2017-06-16

    Applicant: Intel Corporation

    Inventor： Changzheng Wei ,  Weigang Li ,  Cunming Liang

    IPC: G06F21/78 ,  G06F21/44 ,  H04L9/08 ,  G06F21/76

    Abstract: An embodiment of an electronic processing system may include a processor, persistent storage media communicatively coupled to the processor, a reconfigurable device communicatively coupled to the processor over a physically isolated trusted communication channel, a secure provisioner communicatively coupled to the processor and the reconfigurable device to provision a secure storage area and to securely store a remotely generated bitstream security key in the provisioned secure o storage area, and a device configurer to configure the reconfigurable device with a remotely generated bitstream and the remotely generated bitstream security key. Other embodiments are disclosed and claimed.

    Technologies for demoting cache lines to shared cache
    17.
    发明授权
    Technologies for demoting cache lines to shared cache 有权

    公开(公告)号：US10657056B2

    公开(公告)日：2020-05-19

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072 ,  H04L12/933 ,  G06F12/128 ,  G06F13/28

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

    Technologies for internet of things key management
    18.
    发明授权
    Technologies for internet of things key management 有权

    公开(公告)号：US11115193B2

    公开(公告)日：2021-09-07

    申请号：US16649192

    申请日：2017-12-29

    Applicant: INTEL CORPORATION

    Inventor： Changzheng Wei ,  Junyuan Wang ,  Ned Smith ,  Weigang Li ,  Ping Yu

    IPC: H04L9/08 ,  G16Y30/10 ,  H04L9/32 ,  G06F21/45 ,  H04L29/06

    Abstract: Technologies for key management of internet-of-things (IoT) devices include an IoT device, an authority center server, and a group management server. The IoT device is configured to authenticate with an authority center server via an offline communication channel, receive a group member private key as a function of the authentication with the authority center server, and authenticate with a group management server via a secure online communication channel using the group member private key. The IoT device is further configured to receive a group shared key as a function of the authentication with the group management server, encrypt secret data with the group shared key, and transmit the encrypted secret data to the group management server. Other embodiments are described herein.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    20.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    Applicant: Intel Corporation

    Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC: G06F1/32

    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

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