公开(公告)号：US20240071884A1

公开(公告)日：2024-02-29

申请号：US18386913

申请日：2023-11-03

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5381 ,  H01L24/00 ,  H01L25/0655 ,  H01L23/48

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US20190131229A1

公开(公告)日：2019-05-02

申请号：US16219765

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US20180226364A1

公开(公告)日：2018-08-09

申请号：US15749744

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/522 ,  H01L23/544 ,  H01L23/498 ,  H01L23/00 ,  G01R31/27

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20180226331A1

公开(公告)日：2018-08-09

申请号：US15749465

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/58 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/10 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.