公开(公告)号：US11189573B2

公开(公告)日：2021-11-30

申请号：US16069377

申请日：2016-03-31

申请人： Intel Corporation

发明人： Vijay K. Nair ,  Digvijay Raorane

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/78 ,  H01L23/498 ,  H01L21/82

摘要： A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.

公开(公告)号：US11128029B2

公开(公告)日：2021-09-21

申请号：US16335535

申请日：2016-09-26

申请人： Intel Corporation

发明人： Vijay K. Nair ,  Digvijay Raorane

IPC分类号： H01Q1/22 ,  H01L21/48 ,  H01L23/13 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01Q13/00

摘要： Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

公开(公告)号：US20210035881A1

公开(公告)日：2021-02-04

申请号：US16529617

申请日：2019-08-01

申请人： Intel Corporation

发明人： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC分类号： H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

摘要： A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US12068222B2

公开(公告)日：2024-08-20

申请号：US17032577

申请日：2020-09-25

申请人： Intel Corporation

发明人： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane ,  Dingying Xu ,  Ziyin Lin ,  Yiqun Bai

IPC分类号： H01L23/42 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/42 ,  H01L21/481 ,  H01L23/3128

摘要： Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

公开(公告)号：US11798865B2

公开(公告)日：2023-10-24

申请号：US16291314

申请日：2019-03-04

申请人： Intel Corporation

发明人： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11742261B2

公开(公告)日：2023-08-29

申请号：US18089535

申请日：2022-12-27

申请人： Intel Corporation

发明人： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11527489B2

公开(公告)日：2022-12-13

申请号：US16024007

申请日：2018-06-29

申请人： Intel Corporation

发明人： Michael J. Hill ,  Mathew Manusharow ,  Beomseok Choi ,  Digvijay Raorane

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L23/64 ,  G06F1/28 ,  H01F27/28 ,  H01F38/14 ,  H01L25/18

摘要： An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.

公开(公告)号：US20200006166A1

公开(公告)日：2020-01-02

申请号：US16022152

申请日：2018-06-28

申请人： Intel Corporation

发明人： Digvijay Raorane ,  Mathew Manusharow

IPC分类号： H01L23/13 ,  H01L23/64 ,  H01L23/15 ,  H01L23/498

摘要： Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a package substrate; a stiffener having a surface, wherein the stiffener includes a cavity and a conductive pathway between the cavity and the surface of the stiffener, and wherein the stiffener is coupled to the package substrate such that the surface of the stiffener is between the cavity and the package substrate; and an electrical component, wherein the electrical component is embedded in the cavity and is electrically coupled to the package substrate via the conductive pathway.