公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240186227A1

公开(公告)日：2024-06-06

申请号：US18061181

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4605 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K2201/0195

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

公开(公告)号：US20240074046A1

公开(公告)日：2024-02-29

申请号：US17899336

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Karumbu Nathan Meyyappan ,  Dingying Xu

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/11 ,  H05K1/181 ,  H05K3/46 ,  H05K2201/0302 ,  H05K2201/10378

Abstract: Technologies for integrated circuit components with liquid metal interconnects are disclosed. In the illustrative embodiment, a bed of nails socket can mate with an integrated circuit component with liquid metal interconnects. The nails pierce a foam cap layer that seals the liquid metal interconnects, electrically coupling the nails to the liquid metal interconnects. A fabric layer adjacent to the foam cap layer helps secure the foam cap layer, preventing small pieces of the foam cap layer that may be dislodged during repeated insertion into a bed of nails socket from becoming separated from the foam cap layer. The fabric layer can provide additional benefits, such as removing more of the liquid metal from the nails when the integrated circuit component is removed from the bed of nails socket.

公开(公告)号：US20230095281A1

公开(公告)日：2023-03-30

申请号：US17484499

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Hongxia Feng ,  Xiaoying Guo ,  Steve Cho ,  Jung Kyu Han ,  Changhua Liu ,  Leonel Arana ,  Rahul Manepalli ,  Dingying Xu ,  Amram Eitan

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/488 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

公开(公告)号：US09941652B2

公开(公告)日：2018-04-10

申请号：US14973543

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Nachiket R. Raravikar ,  James C. Matayabas, Jr. ,  Akshay Mathkar ,  Dingying Xu

IPC: G01R31/28 ,  H01R43/20 ,  G01R1/073

CPC classification number: H01R43/20 ,  G01R1/07378

Abstract: Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.

公开(公告)号：US09793151B2

公开(公告)日：2017-10-17

申请号：US14568552

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Arjun Krishnan ,  Mohit Mamodia ,  Dingying Xu

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/304 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/78 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

公开(公告)号：US09543197B2

公开(公告)日：2017-01-10

申请号：US13719836

申请日：2012-12-19

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Dingying Xu ,  Yoshihiro Tomita

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2784 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有通过界面层连接到集成电路基板的一个或多个管芯的集成电路（IC）封装的技术和配置。 在一个实施例中，界面层可以包括各向异性部分，其被配置为在诸如管芯和集成电路基板的一个或多个部件之间的面外方向上传导电信号。 在另一个实施例中，界面层可以是介电层或电绝缘层。 在另一个实施例中，界面层可以包括用作两个部件之间的互连的各向异性部分，电介质或绝缘部分，以及由电介质或绝缘部分包围并用作相互之间的互连的一个或多个互连结构 或其他组件。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20250006645A1

公开(公告)日：2025-01-02

申请号：US18343892

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xiao Liu ,  Bohan Shan ,  Dingying Xu ,  Gang Duan ,  Haobo Chen ,  Hongxia Feng ,  Jung Kyu Han ,  Xiaoying Guo ,  Zhixin Xie ,  Xiyu Hu ,  Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Changhua Liu ,  Yosuke Kanaoka

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/58 ,  H01L25/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

公开(公告)号：US20240270929A1

公开(公告)日：2024-08-15

申请号：US18166005

申请日：2023-02-08

Applicant: Intel Corporation

Inventor： Clay Arrington ,  Kyle Arrington ,  Ziyin Lin ,  Jose Waimin ,  Dingying Xu

IPC: C08K3/04 ,  B82Y30/00 ,  B82Y40/00 ,  C08K9/04

CPC classification number: C08K3/041 ,  B82Y30/00 ,  B82Y40/00 ,  C08K9/04 ,  C08K2003/023 ,  C08K2201/011

Abstract: Capillary underfill formulations that may include fillers. The fillers may include carbon nanotubes, such as surface functionalized carbon nanotubes. Methods for forming capillary underfill materials that may have improved fracture toughness, reduced crack propagation, and a reduced likelihood of delamination. The surface functionalized carbon nanotubes may include amine functionalized carbon nanotubes. Containers, such as syringes, that may have a reservoir in which a capillary underfill formulation is disposed.