公开(公告)号：US20210242104A1

公开(公告)日：2021-08-05

申请号：US17234671

申请日：2021-04-19

申请人： Intel Corporation

发明人： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC分类号： H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

摘要： A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11011448B2

公开(公告)日：2021-05-18

申请号：US16529617

申请日：2019-08-01

申请人： Intel Corporation

发明人： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC分类号： H01L23/34 ,  H01L21/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

摘要： A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11749577B2

公开(公告)日：2023-09-05

申请号：US18089536

申请日：2022-12-27

申请人： Intel Corporation

发明人： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49568 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/02371

摘要： A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11581235B2

公开(公告)日：2023-02-14

申请号：US17234671

申请日：2021-04-19

申请人： Intel Corporation

发明人： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC分类号： H01L23/34 ,  H01L21/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

摘要： A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US20220102231A1

公开(公告)日：2022-03-31

申请号：US17032583

申请日：2020-09-25

申请人： Intel Corporation

发明人： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L25/065

摘要： Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.

公开(公告)号：US11239186B2

公开(公告)日：2022-02-01

申请号：US16334965

申请日：2016-09-23

申请人： Intel Corporation

发明人： Digvijay Raorane ,  Vijay K. Nair

IPC分类号： H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01Q1/22 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/13 ,  H01L25/065 ,  G06F1/18 ,  H01L23/48 ,  H01L23/522 ,  H01L23/552

摘要： Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include a substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed on the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

公开(公告)号：US11145583B2

公开(公告)日：2021-10-12

申请号：US15970602

申请日：2018-05-03

申请人： Intel Corporation

发明人： Digvijay Raorane ,  Yidnekachew Mekonnen

IPC分类号： H05K1/02 ,  H05K3/36 ,  H01L23/498 ,  H01L21/48

摘要： Embodiments include packages substrates and a method of forming the package substrate. A package substrate includes a first dielectric comprising a first conductive layer, and a second dielectric comprising a second conductive layer and a third conductive layer. The second and third conductive layers are embedded in the second dielectric, where a top surface of the third conductive layer is above a top surface of the second conductive layer. The package substrate has a fourth conductive layer on the second dielectric. The first dielectric has a first dielectric thickness between the first and third conductive layers. The first dielectric also has a second dielectric thickness between the first and second conductive layers. The package substrate includes the second dielectric thickness that is greater than the first dielectric thickness. The second dielectric may have a z-height of a first bottom surface greater than a z-height of a second bottom surface.

公开(公告)号：US20200006250A1

公开(公告)日：2020-01-02

申请号：US16024007

申请日：2018-06-29

申请人： Intel Corporation

发明人： Michael J. Hill ,  Mathew Manusharow ,  Beomseok Choi ,  Digvijay Raorane

IPC分类号： H01L23/00 ,  H01L23/16 ,  H01L23/64 ,  H01L25/18 ,  H01F27/28 ,  H01F38/14 ,  G06F1/28

摘要： An apparatus may include a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to one or more sides of the substrate. One or more sections of the stiffener may include a magnetic material. The apparatus may further include an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material.

公开(公告)号：US09721906B2

公开(公告)日：2017-08-01

申请号：US14841052

申请日：2015-08-31

申请人： Intel Corporation

发明人： Manish Dubey ,  Rajendra C. Dias ,  Baris Bicen ,  Digvijay Raorane ,  Bharat P. Penmecha

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3142 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/83801 ,  H01L2924/1511 ,  H01L2924/1515 ,  H01L2924/3511

摘要： An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.

公开(公告)号：US20220102242A1

公开(公告)日：2022-03-31

申请号：US17032577

申请日：2020-09-25

申请人： Intel Corporation

发明人： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane ,  Dingying Xu ,  Ziyin Lin ,  Yiqun Bai

IPC分类号： H01L23/42 ,  H01L23/31 ,  H01L21/48

摘要： Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.