公开(公告)号：US09292362B2

公开(公告)日：2016-03-22

申请号：US13926089

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

IPC: G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US11809549B2

公开(公告)日：2023-11-07

申请号：US16728843

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Sagi Meller ,  Gavri Berger ,  Igor Yanover

IPC: G06F21/00 ,  G06F21/54 ,  G06F1/32 ,  G06F21/56 ,  G06F9/38

CPC classification number: G06F21/54 ,  G06F1/32 ,  G06F9/3802 ,  G06F21/561 ,  G06F2221/034

Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

公开(公告)号：US20230273811A1

公开(公告)日：2023-08-31

申请号：US17682091

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Eyal Oz-Sinay ,  Gavri Berger ,  Gal Ofir ,  Tomer Weiner ,  Arkady Bramnik

IPC: G06F9/48 ,  G06F9/22

CPC classification number: G06F9/4843 ,  G06F9/22

Abstract: In one embodiment, an apparatus includes: an instruction fetch circuit to fetch instructions; a decode circuit coupled to the instruction fetch circuit to decode the fetched instructions into micro-operations (pops); a scheduler coupled to the decode circuit to schedule the pops for execution; and an execution circuit coupled to the scheduler, the execution circuit comprising a plurality of execution ports to execute the pops. The scheduler may be configured to: schedule at least some pops of a first type for redundant execution on symmetric execution ports of the plurality of execution ports; and schedule pops of a second type for non-redundant execution on a single execution port of the plurality of execution ports. Other embodiments are described and claimed.

公开(公告)号：US11714875B2

公开(公告)日：2023-08-01

申请号：US16729361

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Amit Gradstein ,  Simon Rubanovich ,  Sagi Meller ,  Saeed Kharouf ,  Gavri Berger ,  Zeev Sperber ,  Jose Yallouz ,  Ron Schneider

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/34

Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits that is switchable to a scheduling mode for execution of a decoded single instruction where the matrix operations accelerator circuit loads a first buffer of the two-dimensional grid of fused multiply accumulate circuits from a first plurality of registers that represents a first input two-dimensional matrix, checks if a second buffer of the two-dimensional grid of fused multiply accumulate circuits stores an immediately prior input two-dimension matrix that is the same as a second input two-dimensional matrix from a second plurality of registers that represents the first input two-dimensional matrix, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits stores the immediately prior input two-dimension matrix, from execution of a previous instruction, that is the same as the second input two-dimensional matrix: prevents reclamation of the second buffer between execution of the previous instruction and the decoded single instruction, performs an operation on the first input two-dimensional matrix from the first buffer and the immediately prior input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in resultant storage, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits does not store the immediately prior input two-dimension matrix, from execution of the previous instruction, that is the same as the second input two-dimensional matrix: loads the second input two-dimensional matrix into the second buffer of the two-dimensional grid of fused multiply accumulate circuits, performs the operation on the first input two-dimensional matrix from the first buffer and the second input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in the resultant storage.

公开(公告)号：US20200310794A1

公开(公告)日：2020-10-01

申请号：US16368973

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： ZEEV SPERBER ,  Amit Gradstein ,  Simon Rubanovich ,  Igor Yanover ,  Gavri Berger ,  Eyal Hadas ,  Saeed Kharouf ,  Ron Schneider ,  Sagi Meller ,  Jose Yallouz

IPC: G06F9/30 ,  G06F9/38

Abstract: The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry. Communication between the RS circuitry 134 and the TMU provides the RS circuitry with notification of successfully executed operations and allows the RS circuitry to cancel operations where the operations are associated with branch mispredictions and/or non-retired speculatively executed instructions.