公开(公告)号：US20180337135A1

公开(公告)日：2018-11-22

申请号：US15776773

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20170179080A1

公开(公告)日：2017-06-22

申请号：US14975128

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Akshay MATHKAR ,  Nachiket Raghunath RARAVIKAR ,  Donald Tiendung TRAN ,  Jerry Lee JENSEN ,  Javier A. FALCON ,  William Nicholas LABANOK ,  Robert Leon SANKMAN ,  Robert Allen STINGEL

IPC: H01L25/065 ,  H01L23/29 ,  H05K1/02 ,  H01L21/56 ,  H01L25/00 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/293 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H05K1/0298 ,  H05K1/115

Abstract: Semiconductor package interposers having high-density and high-aspect ratio encapsulated interconnects, and semiconductor package assemblies incorporating such interposers, are described. In an example, a semiconductor package interposer includes several conductive interconnects encapsulated in a polymer substrate and having height dimensions greater than a cross-sectional dimension. The semiconductor package interposer may support a first semiconductor package above a second semiconductor package and may electrically connect die pins of the first semiconductor package to die pins of the second semiconductor package.