公开(公告)号：US20180331051A1

公开(公告)日：2018-11-15

申请号：US15776021

申请日：2015-12-22

Applicant: Georgios C. DOGLAMIS ,  Telesphor KAMGAING ,  Eric J. LI ,  Javier A. FALCON ,  INTEL CORPORATION

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Eric J. LI, Sr. ,  Javier A. FALCON ,  Yoshihiro TOMITA ,  Vijay K. NAIR ,  Shawna M. LIFF

IPC: H01L23/66 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20220246554A1

公开(公告)日：2022-08-04

申请号：US17721241

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Javier A. FALCON ,  Shawna M. LIFF ,  Yoshihiro TOMITA

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20200212012A1

公开(公告)日：2020-07-02

申请号：US16639085

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Preston T. MEYERS ,  Javier A. FALCON ,  Shawna M. LIFF ,  Joe R. SAUCEDO ,  Adel A. ELSHERBINI ,  Albert S. LOPEZ ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L25/00

Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.

公开(公告)号：US20180240762A1

公开(公告)日：2018-08-23

申请号：US15773033

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Javier A. FALCON ,  Shawna M. LIFF ,  Yoshihiro TOMITA

IPC: H01L23/66 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/48 ,  H01L23/49827 ,  H01L24/00 ,  H01L25/16 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20220344273A1

公开(公告)日：2022-10-27

申请号：US17861125

申请日：2022-07-08

Applicant: Intel Corporation

Inventor： Toshihiro TOMITA ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20200286834A1

公开(公告)日：2020-09-10

申请号：US16879318

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20200227366A1

公开(公告)日：2020-07-16

申请号：US16827296

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Javier A. FALCON ,  Yoshihiro TOMITA ,  Vijay K. NAIR

IPC: H01L23/66 ,  H01L23/00 ,  H01L25/18

Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20240213171A1

公开(公告)日：2024-06-27

申请号：US18596488

申请日：2024-03-05

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20210193583A1

公开(公告)日：2021-06-24

申请号：US17192462

申请日：2021-03-04

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Shawna M. LIFF ,  Henning BRAUNISCH ,  Krishna BHARATH ,  Javier SOTO GONZALEZ ,  Javier A. FALCON

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L23/498

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US20180342472A1

公开(公告)日：2018-11-29

申请号：US15771982

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Javier A. FALCON ,  Yoshihiro TOMITA ,  Vijay K. NAIR

IPC: H01L23/66 ,  H01L23/00 ,  H01L25/18

Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.