公开(公告)号：US10559348B2

公开(公告)日：2020-02-11

申请号：US15980813

申请日：2018-05-16

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Kaushik Vaidyanathan ,  Anant Nori ,  Sreenivas Subramoney ,  Tanay Karnik

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/16 ,  G11C11/4093 ,  G11C11/4091

Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

公开(公告)号：US11411172B2

公开(公告)日：2022-08-09

申请号：US16130912

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Tanay Karnik ,  Ian Young

IPC: G11C11/00 ,  H01L43/04 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18 ,  H01L43/10

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

公开(公告)号：US11043256B2

公开(公告)日：2021-06-22

申请号：US16458022

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Huichu Liu ,  Tanay Karnik ,  Sreenivas Subramoney ,  Jayesh Gaur ,  Sudhanshu Shukla

IPC: G11C11/4096 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/22

Abstract: Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.

公开(公告)号：US11037614B2

公开(公告)日：2021-06-15

申请号：US16615780

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Ian A. Young ,  Tanay Karnik ,  Daniel H. Morris ,  Kaushik Vaidyanathan

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.

公开(公告)号：US10901486B2

公开(公告)日：2021-01-26

申请号：US16384715

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young ,  Tanay Karnik ,  Huichu Liu

IPC: G06F1/3234 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  H03K19/0185

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20190043549A1

公开(公告)日：2019-02-07

申请号：US16144896

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

IPC: G11C11/22 ,  G11C11/413 ,  G06F1/32

Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.