公开(公告)号：US20190230049A1

公开(公告)日：2019-07-25

申请号：US16369889

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L12/933 ,  H01L25/065

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US20240205167A1

公开(公告)日：2024-06-20

申请号：US18587744

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H01L23/538 ,  H01L25/065 ,  H04L49/15

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L23/5386 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US20230208783A1

公开(公告)日：2023-06-29

申请号：US18177417

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H01L25/065 ,  H04L49/15

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L2225/06517 ,  H01L23/5386

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US11916811B2

公开(公告)日：2024-02-27

申请号：US18177417

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H04L49/15 ,  H01L25/065 ,  H01L23/538

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L23/5386 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US10666265B2

公开(公告)日：2020-05-26

申请号：US16146849

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: H03K19/173 ,  G06F7/38 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17704 ,  H03K19/17758

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US20190140648A1

公开(公告)日：2019-05-09

申请号：US16235984

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177 ,  H01L25/065 ,  G11C7/10

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.