公开(公告)号：US20220366630A1

公开(公告)日：2022-11-17

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20200293488A1

公开(公告)日：2020-09-17

申请号：US16354782

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALAPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06T15/00 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180012328A1

公开(公告)日：2018-01-11

申请号：US15204402

申请日：2016-07-07

Applicant: Intel Corporation

Inventor： Jeffery S. Boles ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  PRITAV H. SHAH ,  MICHAEL APODACA ,  MURALI RAMADOSS ,  LALIT K. SAPTARSHI

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.

公开(公告)号：US20170069054A1

公开(公告)日：2017-03-09

申请号：US14846366

申请日：2015-09-04

Applicant: INTEL CORPORATION

Inventor： MURALI RAMADOSS ,  NISHANTH REDDY PENDLURU ,  JEFFREY S. FRIZZELL ,  ANKUR N. SHAH

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: A mechanism is described for facilitating efficient scheduling of graphics workloads at computing devices. A method of embodiments, as described herein, includes receiving a work request for processing a work item at a graphics processor, where the work request is placed by an application. The method may further include allowing the application to directly call into a graphics driver associated with the graphics processor to generate a work queue for the work item, where direct calling allows the application to bypass an intermediary call to the graphics driver and directly submit the work item to the graphics processor, where direct calling further includes notifying the graphics processor of the work unit by writing into a memory location monitored by the graphics processor. The method may further include submitting the work item from the work queue to a submit queue of a plurality of submit queues, where one or more tasks associated with the work item are processed at the graphics processor.

Abstract translation: 描述了用于促进计算设备处的图形工作负载的有效调度的机制。 如本文所述的实施例的方法包括在图形处理器处接收用于处理工作项的工作请求，其中由应用程序放置工作请求。 该方法还可以包括允许应用程序直接调用与图形处理器相关联的图形驱动程序，以生成工作项目的工作队列，其中直接调用允许应用程序绕过对图形驱动器的中间调用并直接提交工作 项目到图形处理器，其中直接呼叫还包括通过写入由图形处理器监视的存储器位置来通知工作单元的图形处理器。 该方法还可以包括将工作项目从工作队列提交到多个提交队列的提交队列，其中与工作项目相关联的一个或多个任务在图形处理器处理。

公开(公告)号：US20160239333A1

公开(公告)日：2016-08-18

申请号：US15025735

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： DAVID J. COWPERTHWAITE ,  MURALI RAMADOSS ,  ANKUR N. SHAH ,  BALAJI VEMBU ,  ALTUG KOKER ,  ADITYA NAVALE

IPC: G06F9/455 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F9/5044 ,  G06F9/5077 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06T1/20 ,  G06T2200/28

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括包括一个或多个GPU引擎的图形处理单元（GPU）和微控制器。 微控制器将为多个虚拟机（VM）中的每一个分配相应的调度时隙。 当特定VM被安排访问第一GPU引擎时，特定VM具有对第一GPU引擎的独占访问。 描述和要求保护其他实施例。