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    APPARATUS AND METHOD FOR SCALABLE ERROR DETECTION AND REPORTING
    2.
    发明申请
    APPARATUS AND METHOD FOR SCALABLE ERROR DETECTION AND REPORTING 审中-公开

    公开(公告)号：US20200167221A1

    公开(公告)日：2020-05-28

    申请号：US16203578

    申请日：2018-11-28

    Applicant: Intel Corporation

    Inventor： BALAJI VEMBU ,  BRYAN WHITE ,  ANKUR SHAH ,  MURALI RAMADOSS ,  DAVE PUFFER ,  ALTUG KOKER ,  ADITYA NAVALE ,  MAHESH NATU

    IPC: G06F11/07 ,  G06T15/00

    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE
    6.
    发明申请
    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE 审中-公开

    公开(公告)号：US20180293690A1

    公开(公告)日：2018-10-11

    申请号：US15482685

    申请日：2017-04-07

    Applicant: Intel Corporation

    Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  BALAJI VEMBU

    IPC: G06T1/20 ,  G06T1/60 ,  G06F12/0875

    CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/621 ,  G06T1/60

    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, one embodiment of an apparatus comprises: a processor comprising one or more cores to execute instructions and process data, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory coupled to the GPU, the GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then the data is to be accessed by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers and wherein requests for the data from the processor cores are processed as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.

    APPARATUS AND METHOD FOR EFFICIENT GRAPHICS VIRTUALIZATION
    7.
    发明申请
    APPARATUS AND METHOD FOR EFFICIENT GRAPHICS VIRTUALIZATION 有权

    公开(公告)号：US20210201556A1

    公开(公告)日：2021-07-01

    申请号：US17141431

    申请日：2021-01-05

    Applicant: Intel Corporation

    Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  BALAJI VEMBU ,  ALTUG KOKER ,  NIRANJAN L. COORAY ,  JOSH B. MASTRONARDE

    IPC: G06T15/00 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G09G5/00 ,  G09G5/393 ,  G06F9/48 ,  G06F9/50

    Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE
    10.
    发明申请
    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE 审中-公开

    公开(公告)号：US20190318446A1

    公开(公告)日：2019-10-17

    申请号：US16365056

    申请日：2019-03-26

    Applicant: Intel Corporation

    Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  BALAJI VEMBU

    IPC: G06T1/20 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06T1/60 ,  G06F12/0811 ,  G06F12/0875

    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

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