中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.014 seconds)

    HARDWARE ASSIST FOR PRIVILEGE ACCESS VIOLATION CHECKS
    4.
    发明申请
    HARDWARE ASSIST FOR PRIVILEGE ACCESS VIOLATION CHECKS 审中-公开

    公开(公告)号：US20170357831A1

    公开(公告)日：2017-12-14

    申请号：US15495644

    申请日：2017-04-24

    Applicant: INTEL CORPORATION

    Inventor： HEMA C. NALLURI ,  ADITYA NAVALE ,  MURALI RAMADOSS

    IPC: G06F21/74 ,  G06F21/84 ,  G06T15/00

    CPC classification number: G06F21/74 ,  G06F21/84 ,  G06T15/005

    Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU

    PROCESS SYNCHRONIZATION BETWEEN ENGINES USING DATA IN A MEMORY LOCATION
    5.
    发明申请
    PROCESS SYNCHRONIZATION BETWEEN ENGINES USING DATA IN A MEMORY LOCATION 审中-公开
    使用存储器位置中的数据的发动机之间的过程同步

    公开(公告)号：US20150287159A1

    公开(公告)日：2015-10-08

    申请号：US14692984

    申请日：2015-04-22

    Applicant: INTEL CORPORATION

    Inventor： HEMA CHAND NALLURI ,  ADITYA NAVALE

    IPC: G06T1/20 ,  G09G5/00 ,  G06F9/52

    CPC classification number: G06T1/20 ,  G06F9/48 ,  G06F9/52 ,  G06F15/167 ,  G09G5/001

    Abstract: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.

    Abstract translation: 描述了基于内存的信号量，其用于在不同处理引擎之间同步进程。 在一个示例中，操作包括在第一处理引擎执行第一处理，执行包括更新存储器寄存器，将信号从第一处理引擎发送到存储器寄存器已被更新的第二处理引擎，该信号包括存储器 寄存器地址以识别更新的存储器寄存器在线数据和数据字，由第二处理引擎从存储器寄存器获取数据，将获取的数据与接收到的数据字进行比较，以及有条件地执行第二处理的下一个命令 基于比较。

    APPARATUS AND METHOD FOR SCALABLE ERROR DETECTION AND REPORTING
    6.
    发明申请
    APPARATUS AND METHOD FOR SCALABLE ERROR DETECTION AND REPORTING 审中-公开

    公开(公告)号：US20200167221A1

    公开(公告)日：2020-05-28

    申请号：US16203578

    申请日：2018-11-28

    Applicant: Intel Corporation

    Inventor： BALAJI VEMBU ,  BRYAN WHITE ,  ANKUR SHAH ,  MURALI RAMADOSS ,  DAVE PUFFER ,  ALTUG KOKER ,  ADITYA NAVALE ,  MAHESH NATU

    IPC: G06F11/07 ,  G06T15/00

    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

    MID-THREAD PRE-EMPTION WITH SOFTWARE ASSISTED CONTEXT SWITCH
    9.
    发明申请
    MID-THREAD PRE-EMPTION WITH SOFTWARE ASSISTED CONTEXT SWITCH 有权
    使用软件辅助的上下文开关进行MID-THREAD预处理

    公开(公告)号：US20160026494A1

    公开(公告)日：2016-01-28

    申请号：US14338729

    申请日：2014-07-23

    Applicant: Intel Corporation

    Inventor： BRIAN D. RAUCHFUSS ,  NAVEEN R. MATAM ,  MICHAEL K. DWYER ,  ADITYA NAVALE

    IPC: G06F9/46 ,  G06F12/10 ,  G06F9/48

    CPC classification number: G06F9/461 ,  G06F9/4812 ,  G06F12/1081 ,  G06F2212/2532

    Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了与软件辅助上下文切换的中线优先级有关的方法和设备。 在一个实施例中，在图形处理单元（GPU）上执行的一个或多个线程响应于预先排除一个或多个线程的请求而以指令级粒度停止。 响应于指令级粒度和/或一个或多个指令的一个或多个线程的完成，一个或多个线程的上下文数据被复制到存储器。 还公开并要求保护其他实施例。

Patent Agency Ranking