公开(公告)号：US20190102229A1

公开(公告)日：2019-04-04

申请号：US15721858

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Russell J. Fenger ,  Vijay Dhanraj ,  Deepak Samuel Kirubakaran ,  Srividya Ambale ,  Israel Hirsh ,  Eliezer Weissmann ,  Hisham Abu-Salah

IPC: G06F9/50

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

公开(公告)号：US20190102227A1

公开(公告)日：2019-04-04

申请号：US15720222

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash Ananthakrishnan ,  Vijay Dhanraj ,  Russell Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth Sistla ,  Guy Therien ,  Ankush Verma ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US12008383B2

公开(公告)日：2024-06-11

申请号：US17008720

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Stephen H. Gunther ,  Russell Fenger

IPC: G06F9/4401 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/4418 ,  G06F9/4405 ,  G06F11/3024 ,  G06F11/3428 ,  G06F11/3466

Abstract: Systems, apparatuses and methods may provide for technology that automatically determines a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis. The technology may also automatically determine a runtime energy efficiency of the heterogeneous processing units, wherein the runtime energy efficiency is determined on a per efficiency class basis. In one example, technology selectively unparks one or more of the heterogeneous processing units based on the runtime performance and the runtime energy efficiency.

公开(公告)号：US20240103914A1

公开(公告)日：2024-03-28

申请号：US17954411

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Russell J. Fenger ,  Rajshree A. Chabukswar ,  Benjamin Graniello ,  Monica Gupta ,  Guy M. Therien ,  Michael W. Chynoweth

IPC: G06F9/48 ,  G06F1/3228

CPC classification number: G06F9/4887 ,  G06F1/3228

Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. Based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. Other embodiments are described and claimed.

公开(公告)号：US20230136365A1

公开(公告)日：2023-05-04

申请号：US18148698

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Mousumi Hazra ,  Javier Martinez ,  Stephen H. Gunther ,  Manuj Sabharwal ,  Michael Voss ,  Derrick Jones ,  Saurabh Tangri ,  Duncan Glendinning

IPC: G06F9/30 ,  G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to allocate accelerator usage. An apparatus to allocate accelerator usage comprises: at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to: store data identifying at least one processing unit in communication with a processing circuitry and at least one class; predict an execution of the at least one processing unit workload based on at least one capability; and schedule which processing unit the workload to run on based on at least one of (i) processor circuitry or (ii) user priority parameters.

公开(公告)号：US11531563B2

公开(公告)日：2022-12-20

申请号：US16912770

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Eliezer Weissmann ,  Hisham Abu Salah ,  Rajshree Arun Chabukswar ,  Russell Jerome Fenger ,  Eugene Gorbatov ,  Guruprasad Settuvalli ,  Balaji Masanamuthu Chinnathurai ,  Sumant Tapas ,  Meghana Gudaram ,  Raj Kumar Subramaniam

IPC: G06F9/48 ,  G06F1/28 ,  G06F9/4401

Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

公开(公告)号：US20220066788A1

公开(公告)日：2022-03-03

申请号：US17008720

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Stephen H. Gunther ,  Russell Fenger

IPC: G06F9/4401 ,  G06F11/30 ,  G06F11/34

Abstract: Systems, apparatuses and methods may provide for technology that automatically determines a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis. The technology may also automatically determine a runtime energy efficiency of the heterogeneous processing units, wherein the runtime energy efficiency is determined on a per efficiency class basis. In one example, technology selectively unparks one or more of the heterogeneous processing units based on the runtime performance and the runtime energy efficiency.

公开(公告)号：US20200272513A1

公开(公告)日：2020-08-27

申请号：US16740794

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.