公开(公告)号：US11990932B2

公开(公告)日：2024-05-21

申请号：US17132893

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Mohamed A. Abdelmoneum ,  Nasser Kurd ,  Thripthi Hegde ,  Narayan Srinivasa ,  Peter Sagazio

IPC: H04B1/692 ,  H04B1/7136 ,  H04B1/7143 ,  H04B1/7156 ,  H04L9/08

CPC classification number: H04B1/7156 ,  H04B1/7136 ,  H04B1/7143 ,  H04L9/0869

Abstract: A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.

公开(公告)号：US11909403B2

公开(公告)日：2024-02-20

申请号：US16870405

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Kuan-Yueh Shen ,  Nasser Kurd

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/07 ,  H03K5/156 ,  H03L7/087

CPC classification number: H03L7/0814 ,  H03K5/1565 ,  H03L7/07 ,  H03L7/087 ,  H03L7/0818

Abstract: A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

公开(公告)号：US11188117B2

公开(公告)日：2021-11-30

申请号：US16637646

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Nasser Kurd

IPC: G06F1/10 ,  H03L7/093 ,  H03L7/099

Abstract: An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

公开(公告)号：US09876491B2

公开(公告)日：2018-01-23

申请号：US14929154

申请日：2015-10-30

Applicant: INTEL CORPORATION

Inventor： Mark Neidengard ,  Vaughn Grossnickle ,  Nasser Kurd ,  Jeffrey Krieger

IPC: H03K5/156 ,  H03K3/03

CPC classification number: H03K5/1565 ,  H03K3/0315

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

公开(公告)号：US20160327974A1

公开(公告)日：2016-11-10

申请号：US15212044

申请日：2016-07-15

Applicant: Intel Corporation

Inventor： Allan Feldman ,  Nasser Kurd ,  Mark Neidengard ,  Vaughn Grossnickle ,  Praveen Mosalikanti

IPC: G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/04 ,  G06F1/08 ,  H03K5/15 ,  H03L7/06 ,  H03L7/08 ,  H03L7/0802 ,  H03L7/083

Abstract: In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

Abstract translation: 在一些实施例中，提供紧密环路模式，其中大多数（如果不是全部）时钟分配电路可能在初始频率锁定阶段期间被旁路。

公开(公告)号：US20150214959A1

公开(公告)日：2015-07-30

申请号：US14126005

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Allan Feldman ,  Nasser Kurd ,  Mark Neidengard ,  Vaughn Grossnickle ,  Praveen Mosalikanti

IPC: H03L7/08 ,  H03L7/083

CPC classification number: G06F1/10 ,  G06F1/04 ,  G06F1/08 ,  H03K5/15 ,  H03L7/06 ,  H03L7/08 ,  H03L7/0802 ,  H03L7/083

Abstract: In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

Abstract translation: 在一些实施例中，提供紧密环路模式，其中大多数（如果不是全部）时钟分配电路可以在初始频率锁定阶段期间被旁路。

公开(公告)号：US20140218088A1

公开(公告)日：2014-08-07

申请号：US13993137

申请日：2011-12-15

Applicant: INTEL CORPORATION

Inventor： Mark Neidengaed ,  Vaughn Grossnickle ,  Nasser Kurd ,  Jeffrey Krieger

IPC: H03K5/04

CPC classification number: H03K5/04 ,  G06F1/04

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Abstract translation: 这里描述了用于重新合成时钟信号的装置，方法和系统。 该装置包括：第一逻辑单元，用于检测输入时钟信号的上升沿，并且用于基于检测到的输入时钟信号的上升沿产生输出时钟信号的上升沿，所述输入时钟信号具有非50 占空比的百分之一和第一期; 以及第二逻辑单元，用于根据检测到的输入时钟信号的上升沿计算输出时钟信号的下降沿，输出时钟信号的下降沿接近第一周期的一半。