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    Chevron interconnect for very fine pitch probing
    13.
    发明授权
    Chevron interconnect for very fine pitch probing 有权

    公开(公告)号：US11268983B2

    公开(公告)日：2022-03-08

    申请号：US15640415

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Pooya Tadayon

    IPC: G01R1/067 ,  G01R31/28 ,  G01R1/073

    Abstract: An apparatus an apparatus comprising: a substrate having a plane; and an array of at least one conductive probe having a base affixed to the substrate, the at least one conductive probe having a major axis extending from the plane of the substrate and terminating at a tip, wherein the one or more conductive probes comprise at least three points that are non-collinear.

    MULTI-MEMBER TEST PROBE STRUCTURE
    14.
    发明申请
    MULTI-MEMBER TEST PROBE STRUCTURE 有权

    公开(公告)号：US20210302489A1

    公开(公告)日：2021-09-30

    申请号：US17343648

    申请日：2021-06-09

    Applicant: Intel Corporation

    Inventor： Pooya Tadayon ,  Justin Huttula

    IPC: G01R31/28 ,  G01R3/00 ,  G01R1/067

    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.

    Converged test platforms and processes for class and system testing of integrated circuits
    16.
    发明授权
    Converged test platforms and processes for class and system testing of integrated circuits 有权

    公开(公告)号：US10677845B2

    公开(公告)日：2020-06-09

    申请号：US15447095

    申请日：2017-03-01

    Applicant: Intel Corporation

    Inventor： Abram M. Detofsky ,  Evan M. Fledell ,  Mustapha A. Abdulai ,  John M. Peterson ,  Dinia P. Kitendaugh ,  Pooya Tadayon ,  Jin Pan ,  David Shia

    IPC: G01R31/319 ,  G01R31/28

    Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

    COOLING APPARATUSES FOR MICROELECTRONIC ASSEMBLIES
    17.
    发明申请
    COOLING APPARATUSES FOR MICROELECTRONIC ASSEMBLIES 审中-公开

    公开(公告)号：US20190385925A1

    公开(公告)日：2019-12-19

    申请号：US16012126

    申请日：2018-06-19

    Applicant: Intel Corporation

    Inventor： Joe F. Walczyk ,  Pooya Tadayon

    IPC: H01L23/367 ,  H01L21/48 ,  H01L23/46

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

    Double-sided substrate with cavities for direct die-to-die interconnect
    19.
    发明授权
    Double-sided substrate with cavities for direct die-to-die interconnect 有权

    公开(公告)号：US12230610B2

    公开(公告)日：2025-02-18

    申请号：US18377639

    申请日：2023-10-06

    Applicant: Intel Corporation

    Inventor： Pooya Tadayon

    IPC: H01L25/065 ,  H01L23/13 ,  H01L23/538

    Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

    Hybrid thermal interface material (TIM) with reduced 3D thermal resistance
    20.
    发明授权
    Hybrid thermal interface material (TIM) with reduced 3D thermal resistance 有权

    公开(公告)号：US12087658B2

    公开(公告)日：2024-09-10

    申请号：US16889562

    申请日：2020-06-01

    Applicant: INTEL CORPORATION

    Inventor： Pooya Tadayon ,  Joe Walczyk

    IPC: H01L23/373 ,  H01L23/42 ,  H01L23/40

    CPC classification number: H01L23/3733 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/4006

    Abstract: A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

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