公开(公告)号：US11043158B2

公开(公告)日：2021-06-22

申请号：US15863396

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Paul Diefenbaugh ,  Sameer Kalathil Perazhi ,  Fong-Shek Lam ,  Arthur Jeremy Runyan ,  Jason Tanner

IPC: G09G3/20 ,  G06T1/60 ,  G06F3/14 ,  G06T9/00 ,  H04N19/426

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

公开(公告)号：US20190102861A1

公开(公告)日：2019-04-04

申请号：US15721273

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Arthur J. Runyan

IPC: G06T1/60 ,  G09G5/395

CPC classification number: G06T1/60 ,  G06T1/20 ,  G09G5/363 ,  G09G5/395 ,  G09G2320/0257 ,  G09G2330/026 ,  G09G2330/08 ,  G09G2330/12 ,  G09G2354/00 ,  G09G2360/12 ,  G09G2360/127 ,  G09G2360/18 ,  G09G2380/10

Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.

公开(公告)号：US12164370B2

公开(公告)日：2024-12-10

申请号：US18302999

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Bradley T. Coffman ,  Gustavo P. Espinosa ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/00 ,  G05F1/56 ,  G05F1/575 ,  G06F1/30 ,  G06F11/07 ,  G06F11/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

公开(公告)号：US11669385B2

公开(公告)日：2023-06-06

申请号：US16556565

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Bradley T. Coffman ,  Gustavo P. Espinosa ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F1/30 ,  G05F1/56 ,  G05F1/575

CPC classification number: G06F11/0793 ,  G05F1/562 ,  G05F1/575 ,  G06F1/30 ,  G06F11/3058

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

公开(公告)号：US20190052286A1

公开(公告)日：2019-02-14

申请号：US15938505

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Gustavo P. Espinosa ,  Daren J. Schmidt

IPC: H03M13/01 ,  G06F11/10 ,  G11C29/52 ,  B60W50/02

CPC classification number: H03M13/015 ,  B60W50/0205 ,  B60W2050/0005 ,  B60W2050/021 ,  G06F11/10 ,  G06F11/1068 ,  G06F11/2215 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.