公开(公告)号：US10956813B2

公开(公告)日：2021-03-23

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Gregory K. Chen ,  Amrita Mathuriya ,  Abhishek Sharma ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/419 ,  G11C5/06 ,  H03M7/30 ,  G11C11/413 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

公开(公告)号：US20200312404A1

公开(公告)日：2020-10-01

申请号：US16417538

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

IPC: G11C11/419 ,  H04L9/32

Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

公开(公告)号：US20200104101A1

公开(公告)日：2020-04-02

申请号：US16143770

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Sanu Mathew ,  Vikram Suresh ,  Raghavan Kumar

IPC: G06F7/58 ,  G06F21/75 ,  H04L9/32

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

公开(公告)号：US20190205730A1

公开(公告)日：2019-07-04

申请号：US16299014

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Huseyin E. SUMBUL ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US20190042909A1

公开(公告)日：2019-02-07

申请号：US15821123

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

公开(公告)号：US12137169B2

公开(公告)日：2024-11-05

申请号：US17854911

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/00 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US12047485B2

公开(公告)日：2024-07-23

申请号：US17132365

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Xiaosen Liu ,  Harish Krishnamurthy ,  Sanu Mathew ,  Vikram Suresh

IPC: H04L9/00 ,  G05F1/46 ,  G05F1/575 ,  G05F1/59 ,  G06F1/26 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/003 ,  G06F1/26 ,  H04L9/0631 ,  H04L2209/08

Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

公开(公告)号：US11768966B2

公开(公告)日：2023-09-26

申请号：US17930326

申请日：2022-09-07

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Raghavan Kumar ,  Sanu Mathew

IPC: G06F21/44 ,  G06F21/73 ,  G06F21/75 ,  G06F21/31 ,  G06F21/79

CPC classification number: G06F21/75 ,  G06F21/31 ,  G06F21/79 ,  G06F2221/2103

Abstract: A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

公开(公告)号：US11663452B2

公开(公告)日：2023-05-30

申请号：US16583217

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram Krishnamurthy ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Deepak Vinayak Kadetotad

IPC: G06F17/16 ,  G06N3/063 ,  G06F7/544 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06F17/16 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

公开(公告)号：US11456877B2

公开(公告)日：2022-09-27

申请号：US16456187

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Vikram Suresh ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  G06F21/76 ,  H04L9/08

Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments. A method includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.