公开(公告)号：US10944428B2

公开(公告)日：2021-03-09

申请号：US16398003

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Poovaiah Palangappa ,  Santhosh Vanaparthy

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/37 ,  H03M13/39 ,  G06F11/10 ,  G06F11/07

Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.

公开(公告)号：US20190188073A1

公开(公告)日：2019-06-20

申请号：US16282725

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Ravi Motwani

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/39

CPC classification number: G06F11/108 ,  G06F11/1004 ,  G06F11/1044 ,  G06F11/1048 ,  H03M13/1102 ,  H03M13/3927

Abstract: Embodiments are directed towards apparatuses, methods, and systems for a codeword distribution manager to divide a codeword into portions to be written to individual storage units and read from the corresponding different individual storage units to reduce a raw bit error rate (RBER) related to storage of the codeword. In embodiments, the codeword distribution manager is included in a memory controller and the plurality of individual storage units are coupled to the memory controller and include individual memory die or individual pages of a memory die. In embodiments, the codeword is a single codeword and includes encoded data and an error correction code. In some embodiments, the codeword includes a low density parity data check code (LDPC). Additional embodiments may be described and claimed.

公开(公告)号：US20190074851A1

公开(公告)日：2019-03-07

申请号：US16173293

申请日：2018-10-29

Applicant: Intel Corporation

Inventor： Ravi Motwani

IPC: H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15

Abstract: An embodiment of a semiconductor apparatus may include technology to store a first portion of a code for a tile in a first die of the two or more nonvolatile memory die, store a second portion of the code for the tile in a second die of the two or more nonvolatile memory die, and perform an exclusive-or operation to correct a data error in the tile based on the stored first and second portions of the code. Other embodiments are disclosed and claimed.