公开(公告)号：US20220108743A1

公开(公告)日：2022-04-07

申请号：US17551116

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Chang Kian TAN ,  Kuljit S. BAINS ,  Saravanan SETHURAMAN

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4093

Abstract: An apparatus is described. The apparatus includes a memory controller having a network interface and a channel interface. The channel interface is to send read, write and refresh commands into a region of a memory. The network interface is to receive memory access requests from a network, wherein the memory requests target the region of the memory. The memory requests are sent into the network by one or more host interfaces. The memory controller has bank refresh logic circuitry. The memory controller has signaling logic circuitry to send a back pressure signal to the one or more host interfaces. The back pressure signal identifies a bank of the region of the memory that is about to be refreshed by the bank refresh logic circuitry. The back pressure signal is to inform the one or more host interfaces that any memory requests that target the bank will not be serviced by the region of memory before the bank begins to be refreshed.

公开(公告)号：US20240241842A1

公开(公告)日：2024-07-18

申请号：US18622902

申请日：2024-03-30

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  Caroline GRIMES

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F9/30189 ,  G06F13/4243

Abstract: Training a physical interface between a memory device and a memory controller can be performed with an autonomous sweep. The sweep can occur without commands from the host to trigger each parameter sweep. With a two dimensional sweep, instead of interrupting a training mode for a first parameter to sweep a second parameter, circuitry in the memory can automatically sweep the second parameter in the training mode for the first parameter.

公开(公告)号：US20230125412A1

公开(公告)日：2023-04-27

申请号：US18086639

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

IPC: G11C7/10 ,  G11C7/22

Abstract: An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

公开(公告)号：US20230044892A1

公开(公告)日：2023-02-09

申请号：US17969518

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Xiang LI ,  Saravanan SETHURAMAN ,  George VERGIS ,  James A. McCALL

IPC: H05K1/11 ,  H01L25/18 ,  H05K1/18

Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

公开(公告)号：US20220190844A1

公开(公告)日：2022-06-16

申请号：US17688125

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Tonia M. ROSE ,  Saravanan SETHURAMAN

IPC: H03M13/09 ,  G06F13/16 ,  H03M13/00

Abstract: A differential Data Strobe (DQS) signal is used to transmit and receive Cyclic Redundancy Check (CRC) between a host memory controller and a memory module. The differential DQS strobe signal is trained before it is used for transactions. The training is performed by sending and receiving a CRC pattern on the differential DQS strobe signal between the host memory controller and a buffer in the memory module.