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公开(公告)号：US20220262070A1
公开(公告)日：2022-08-18
申请号：US17590521
申请日：2022-02-01
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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公开(公告)号：US11263720B2
公开(公告)日：2022-03-01
申请号：US16985329
申请日：2020-08-05
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US20210349717A1
公开(公告)日：2021-11-11
申请号：US16914030
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Chandra Gurram , Subramaniam Maiyuran , Supratim Pal , Saurabh Sharma , Aditya Navale
Abstract: Described herein is an accelerator device in which compaction of diverged lanes of a parallel processor is enabled to increase the efficiency of ALU utilization. One embodiment provides an accelerator device comprising a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including a parallel processing architecture configured to enable compaction of diverged lanes.
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公开(公告)号：US20210217235A1
公开(公告)日：2021-07-15
申请号：US17154174
申请日：2021-01-21
Applicant: Intel Corporation
Inventor： Justin DeCell , Saurabh Sharma , Subramaniam Maiyuran , Raghavendra Miyar , Jorge Garcia Pabon
Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
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公开(公告)号：US20210035257A1
公开(公告)日：2021-02-04
申请号：US16985329
申请日：2020-08-05
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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Patent Agency Ranking
公开(公告)号：US10748242B2
公开(公告)日：2020-08-18
申请号：US16046650
申请日：2018-07-26
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G09G5/00 , G06T1/60 , G06F12/0875 , G06T1/20
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US20180293695A1
公开(公告)日：2018-10-11
申请号：US15483236
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US20180286011A1
公开(公告)日：2018-10-04
申请号：US15477039
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G06T1/60 , G06T1/20 , G06F12/0875
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US09836809B2
公开(公告)日：2017-12-05
申请号：US14866437
申请日：2015-09-25
Applicant: Intel Corporation
CPC classification number: G06T1/20 , G06F11/1453 , G06F17/3033 , G06T1/60
Abstract: An apparatus and method for adaptive pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first lookup in a first data structure to identify a second data structure; performing a second lookup in the second data structure using the X and Y coordinates for the pixel block to identify a third data structure; performing a third lookup in a third data structure indexed based on the X and Y coordinates of the pixel block, the third lookup identifying an entry in the third data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and processing the pixel block by the execution cluster.
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公开(公告)号：US20210407194A1
公开(公告)日：2021-12-30
申请号：US16914783
申请日：2020-06-29
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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