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公开(公告)号：US20200301825A1
公开(公告)日：2020-09-24
申请号：US15930889
申请日：2020-05-13
Applicant: Intel Corporation
Inventor： Chetan Chauhan , Sourabh Dongaonkar , Rajesh Sundaram , Jawad Khan , Sandeep Guliani , Dipanjan Sengupta , Mariano Tepper
Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.
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公开(公告)号：US20200266929A1
公开(公告)日：2020-08-20
申请号：US16867638
申请日：2020-05-06
Applicant: Intel Corporation
Inventor： Wei Wu , Sourabh Dongaonkar , Jawad Khan
Abstract: Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.
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Patent Agency Ranking
公开(公告)号：US12265724B2
公开(公告)日：2025-04-01
申请号：US17337314
申请日：2021-06-02
Applicant: Intel Corporation
Inventor： Sourabh Dongaonkar , Jawad B. Khan
IPC: G06F3/06
Abstract: Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the matrix comprises one or more columns and/or one or more rows. In some examples, the memory device comprises one or more of: a three-dimensional (3D) cross point memory device, volatile memory device, or non-volatile memory device.
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14.发明授权公开(公告)号：US11604834B2
公开(公告)日：2023-03-14
申请号：US16870003
申请日：2020-05-08
Applicant: Intel Corporation
Inventor： Mariano Tepper , Dipanjan Sengupta , Sourabh Dongaonkar , Chetan Chauhan , Jawad Khan , Theodore Willke , Richard Coulson , Rajesh Sundaram
IPC: G06F16/903 , G06F17/16 , G06K9/62
Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.
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公开(公告)号：US11327881B2
公开(公告)日：2022-05-10
申请号：US15930889
申请日：2020-05-13
Applicant: Intel Corporation
Inventor： Chetan Chauhan , Sourabh Dongaonkar , Rajesh Sundaram , Jawad Khan , Sandeep Guliani , Dipanjan Sengupta , Mariano Tepper
Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.
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公开(公告)号：US20200265045A1
公开(公告)日：2020-08-20
申请号：US16868069
申请日：2020-05-06
Applicant: Intel Corporation
Inventor： Mariano Tepper , Dipanjan Sengupta , Jawad Khan , Sourabh Dongaonkar , Chetan Chauhan , Richard Coulson , Theodore Willke
IPC: G06F16/2458 , G06F16/248 , G06N20/00 , G06N7/00
Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.
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17.发明申请公开(公告)号：US20200264874A1
公开(公告)日：2020-08-20
申请号：US16867948
申请日：2020-05-06
Applicant: Intel Corporation
Inventor： Mariano Tepper , Dipanjan Sengupta , Sourabh Dongaonkar , Chetan Chauhan , Jawad Khan , Theodore Willke , Richard Coulson
Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.
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