公开(公告)号：US12237040B2

公开(公告)日：2025-02-25

申请号：US17468210

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad B. Khan ,  Sandeep K. Guliani ,  William K. Waller

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/14

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

公开(公告)号：US11258539B2

公开(公告)日：2022-02-22

申请号：US16867638

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Wei Wu ,  Sourabh Dongaonkar ,  Jawad Khan

IPC: H04L1/00 ,  H04L1/06 ,  H03M13/11

Abstract: Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.

公开(公告)号：US20200301828A1

公开(公告)日：2020-09-24

申请号：US16894180

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Jawad Khan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Sourabh Dongaonkar ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/40

Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.

公开(公告)号：US20200265098A1

公开(公告)日：2020-08-20

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06K9/62 ,  G06F17/16

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US11829376B2

公开(公告)日：2023-11-28

申请号：US16868069

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Jawad Khan ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Richard Coulson ,  Theodore Willke

IPC: G06F16/2458 ,  G06N20/00 ,  G06F16/248 ,  G06N7/01

CPC classification number: G06F16/2462 ,  G06F16/248 ,  G06N7/01 ,  G06N20/00

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

公开(公告)号：US11500887B2

公开(公告)日：2022-11-15

申请号：US17227045

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Jawad B. Khan ,  Chetan Chauhan ,  Dipanjan Sengupta ,  Mariano Tepper ,  Theodore Willke ,  Richard L. Coulson

IPC: G06F16/24 ,  G06F16/2458 ,  G06N7/00 ,  G06F16/21 ,  G06F16/22 ,  G06F16/248

Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.

公开(公告)号：US20210286549A1

公开(公告)日：2021-09-16

申请号：US17327266

申请日：2021-05-21

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Jawad Khan

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that organizes data and corresponding parity information into a plurality of die words, distributes a column of the die words across a plurality of storage dies, and distributes the column across a plurality of partitions. In one example, the technology also reads a row of the die words at a read rate and reads the column of the die words at the read rate.

公开(公告)号：US11989553B2

公开(公告)日：2024-05-21

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F16/23 ,  G06F7/58 ,  G06F9/30 ,  G06F16/13 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/9535 ,  G06F16/9538 ,  H01L27/06

CPC classification number: G06F9/3001 ,  G06F7/58 ,  G06F9/30036 ,  G06F16/137 ,  G06F16/2255 ,  H01L27/0688

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

公开(公告)号：US20230305709A1

公开(公告)日：2023-09-28

申请号：US18040145

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Mariano Tepper ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

公开(公告)号：US20220350525A1

公开(公告)日：2022-11-03

申请号：US17866165

申请日：2022-07-15

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Shigeki Tomishima ,  Jawad Khan

IPC: G06F3/06

Abstract: An example of an apparatus may include memory organized as at least one bank that includes two or more arrays, and circuitry communicatively coupled to the memory to select respective rows of the two or more arrays of a bank for a memory access operation based on an access orientation signal. Other examples are disclosed and claimed.