公开(公告)号：US11024380B2

公开(公告)日：2021-06-01

申请号：US16685719

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

公开(公告)号：US09852789B2

公开(公告)日：2017-12-26

申请号：US15333096

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Sandeep Guliani ,  Balaji Srinivasan ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/70

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

公开(公告)号：US09478286B1

公开(公告)日：2016-10-25

申请号：US14998179

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Sandeep Guliani ,  Balaji Srinivasan ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/70

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract translation: 提供并讨论了通过绝缘和修复电流机制（包括相关系统和方法）演示瞬态电流保护的阈值开关器件。

公开(公告)号：US10438659B2

公开(公告)日：2019-10-08

申请号：US16037255

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20170236580A1

公开(公告)日：2017-08-17

申请号：US15046339

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.

公开(公告)号：US11327881B2

公开(公告)日：2022-05-10

申请号：US15930889

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Sourabh Dongaonkar ,  Rajesh Sundaram ,  Jawad Khan ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/02 ,  G06F16/27

Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.

公开(公告)号：US20200160908A1

公开(公告)日：2020-05-21

申请号：US16685719

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

公开(公告)号：US10482960B2

公开(公告)日：2019-11-19

申请号：US15046339

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

公开(公告)号：US10032508B1

公开(公告)日：2018-07-24

申请号：US15396224

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20180190353A1

公开(公告)日：2018-07-05

申请号：US15396224

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/12 ,  G11C2213/71

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.