公开(公告)号：US11989553B2

公开(公告)日：2024-05-21

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F16/23 ,  G06F7/58 ,  G06F9/30 ,  G06F16/13 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/9535 ,  G06F16/9538 ,  H01L27/06

CPC classification number: G06F9/3001 ,  G06F7/58 ,  G06F9/30036 ,  G06F16/137 ,  G06F16/2255 ,  H01L27/0688

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

公开(公告)号：US20230305709A1

公开(公告)日：2023-09-28

申请号：US18040145

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Mariano Tepper ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

公开(公告)号：US20200301825A1

公开(公告)日：2020-09-24

申请号：US15930889

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Sourabh Dongaonkar ,  Rajesh Sundaram ,  Jawad Khan ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/02 ,  G06F16/27

Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.

公开(公告)号：US11853766B2

公开(公告)日：2023-12-26

申请号：US17872927

申请日：2022-07-25

Applicant: Intel Corporation

Inventor： Vy Vo ,  Dipanjan Sengupta ,  Mariano Tepper ,  Javier Sebastian Turek

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/50 ,  G06F12/0815 ,  G06N3/063 ,  G06F11/34 ,  G06F18/21 ,  G06N3/045

CPC classification number: G06F9/3877 ,  G06F9/321 ,  G06F9/5016 ,  G06F9/5066 ,  G06F11/3457 ,  G06F12/0815 ,  G06F18/217 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1021

Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.

公开(公告)号：US11604834B2

公开(公告)日：2023-03-14

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06F17/16 ,  G06K9/62

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US11327881B2

公开(公告)日：2022-05-10

申请号：US15930889

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Sourabh Dongaonkar ,  Rajesh Sundaram ,  Jawad Khan ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/02 ,  G06F16/27

Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.

公开(公告)号：US20200327365A1

公开(公告)日：2020-10-15

申请号：US16914303

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Theodore Willke ,  Javier Sebastian Turek

IPC: G06K9/62 ,  G06N20/00 ,  H04L9/06

Abstract: Systems, apparatuses and methods may store a plurality of classes that represent a plurality of clusters in a cache. Each of the classes represents a group of the plurality of clusters and the plurality of clusters is in a first data format. The systems, apparatuses and methods further modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one class of the classes.

公开(公告)号：US20200326949A1

公开(公告)日：2020-10-15

申请号：US16914293

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Vy Vo ,  Dipanjan Sengupta ,  Mariano Tepper ,  Javier Sebastian Turek

IPC: G06F9/32 ,  G06F9/50 ,  G06F12/0815 ,  G06F11/34 ,  G06K9/62 ,  G06N3/063 ,  G06N3/04

Abstract: Systems, apparatuses and methods may provide for technology that recognizes, via a neural network, a pattern of memory access and compute instructions based on an input set of machine instructions, determines, via a neural network, a sequence of instructions to be offloaded for execution by the secondary computing device based on the recognized pattern of memory access and compute instructions, and translates the sequence of instructions to be offloaded from instructions executable by a central processing unit (CPU) into instructions executable by the secondary computing device.

公开(公告)号：US20200265045A1

公开(公告)日：2020-08-20

申请号：US16868069

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Jawad Khan ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Richard Coulson ,  Theodore Willke

IPC: G06F16/2458 ,  G06F16/248 ,  G06N20/00 ,  G06N7/00

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

公开(公告)号：US20200264874A1

公开(公告)日：2020-08-20

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F9/30 ,  G06F7/58 ,  G06F16/13 ,  H01L27/06

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.