公开(公告)号：US09824754B2

公开(公告)日：2017-11-21

申请号：US15000643

申请日：2016-01-19

Applicant: INTEL CORPORATION

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

公开(公告)号：US09747041B2

公开(公告)日：2017-08-29

申请号：US14757926

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0866

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US09449671B2

公开(公告)日：2016-09-20

申请号：US14132987

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

IPC: G11C7/02 ,  G11C11/406 ,  G06F13/16

CPC classification number: G11C7/02 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

Abstract translation: 公开了用于概率动态随机存取存储器（DRAM）行修复的示例。 在一些示例中，使用DRAM的行敲击限制和DRAM的最大激活率可以确定概率行锤检测值。 然后可以使用概率行锤检测值，使得概率可接受地低，以致对DRAM的侵入行进行的给定激活导致在对一个或多个受害行进行相关联的调度行刷新之前超过行敲击限制 与侵略者行。 其他的例子被描述和要求保护。