公开(公告)号：US09443567B1

公开(公告)日：2016-09-13

申请号：US14688990

申请日：2015-04-16

Applicant: Intel Corporation

Inventor： Pankaj Vinayak Dudulwar ,  Chenchu Punnarao Bandi ,  Lip Khoon Teh ,  Tat Hin Tan

IPC: G11C7/06 ,  H04B1/16

CPC classification number: H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1078 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

Abstract translation: 描述了一种装置，包括：用于感测相对于另一信号的输入信号的输入感测级; 耦合到输入感测级的判定电路，用于确定输入信号是逻辑低还是逻辑高; 以及耦合到输入感测级和决策电路的电源管理电路，其可操作以监视决策电路的状态并根据监视状态禁用输入感测级。 描述了一种装置，其包括：与输入感测级集成的决策电路，其中所述决策电路可操作以在所述时钟信号的相位期间对其内部节点进行预充电; 以及锁存电路，用于锁存所述决策电路的输出。

公开(公告)号：US12080628B2

公开(公告)日：2024-09-03

申请号：US18132801

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/09 ,  H01L24/17 ,  H01L25/16 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US10903142B2

公开(公告)日：2021-01-26

申请号：US16402482

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Tat Hin Tan ,  Wai Ling Lee

IPC: H01L23/02 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822 ,  H01L49/02

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US10223483B1

公开(公告)日：2019-03-05

申请号：US15390322

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  William Walter Fergusson ,  Chieu Fung Tan

IPC: G06F17/50 ,  G06F11/34

Abstract: A methodology for defining resistance-capacitance (RC) design targets based on radio-frequency (RF) simulation is provided. In particular, the method may involve first determining capacitance targets and then determining resistance targets. To compute the capacitance targets, integrate circuit design and simulations tools may run transient analysis to identify critical nodes, perform small signal and sensitivity analysis for the capacitance on the critical nodes, revise original RF specifications by allocating additional margin, and perform interpolation among multiple capacitance values to obtain capacitive design targets that meet the revised specifications. To compute the resistance targets, the circuit design tools may identify critical transistors, run single-pass and DC operating point simulation to determine initial resistance values for the critical transistors, simplify parallel resistive networks, perform sensitivity analysis on the simplified networks, and perform interpolation among multiple resistive values to obtain resistive design targets meet the original RF performance specifications.