公开(公告)号：US20190114194A1

公开(公告)日：2019-04-18

申请号：US16211934

申请日：2018-12-06

申请人： Intel Corporation

发明人： Nrupal JANI ,  Manasi DEVAL ,  Anjali SINGHAI ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Neerav PARIKH ,  Alexander H. DUYCK ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC分类号： G06F9/455

摘要： Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.

公开(公告)号：US20190108106A1

公开(公告)日：2019-04-11

申请号：US16211955

申请日：2018-12-06

申请人： Intel Corporation

发明人： Mitu AGGARWAL ,  Nrupal JANI ,  Manasi DEVAL ,  Kiran PATIL ,  Parthasarathy SARANGAM ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC分类号： G06F11/20 ,  G06F13/40 ,  G06F15/173

摘要： Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.

公开(公告)号：US20240127392A1

公开(公告)日：2024-04-18

申请号：US17967768

申请日：2022-10-17

申请人： Intel Corporation

发明人： Christopher J. HUGHES ,  Saurabh GAYEN ,  Utkarsh Y. KAKAIYA ,  Alexander F. HEINECKE

IPC分类号： G06T1/60 ,  G06T1/20

CPC分类号： G06T1/60 ,  G06T1/20

摘要： A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, generate first intermediate data, and store the first intermediate data to a storage. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data from the storage, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

公开(公告)号：US20200174841A1

公开(公告)日：2020-06-04

申请号：US16619442

申请日：2017-06-29

申请人： INTEL CORPORATION

发明人： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC分类号： G06F9/50 ,  G06F9/46 ,  G06F9/48

摘要： A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20200012530A1

公开(公告)日：2020-01-09

申请号：US16351396

申请日：2019-03-12

申请人： Intel Corporation

发明人： Utkarsh Y. KAKAIYA ,  Rajesh SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

IPC分类号： G06F9/50 ,  H04L12/58

摘要： Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20190114196A1

公开(公告)日：2019-04-18

申请号：US16211950

申请日：2018-12-06

申请人： Intel Corporation

发明人： Mitu AGGARWAL ,  Nrupal JANI ,  Manasi DEVAL ,  Kiran PATIL ,  Parthasarathy SARANGAM ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC分类号： G06F9/455 ,  G06F9/48

摘要： Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.

公开(公告)号：US20190107965A1

公开(公告)日：2019-04-11

申请号：US16211930

申请日：2018-12-06

申请人： Intel Corporation

发明人： Manasi DEVAL ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/42

摘要： Examples may include a method of protecting memory and I/O transactions. The method includes allocating memory for an application, assigning a resource of a physical device to the application, assigning a process address space identifier to the assigned resource, creating a security enclave to protect the allocated memory of the application, and associating the security enclave with the process address space identifier to protect the allocated memory and the assigned resource.

公开(公告)号：US20240126613A1

公开(公告)日：2024-04-18

申请号：US17967740

申请日：2022-10-17

申请人： Intel Corporation

发明人： Saurabh GAYEN ,  Christopher J. HUGHES ,  Utkarsh Y. KAKAIYA ,  Alexander F. HEINECKE

IPC分类号： G06F9/50 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/505 ,  G06F9/3555 ,  G06F9/3877

摘要： A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

公开(公告)号：US20230070995A1

公开(公告)日：2023-03-09

申请号：US17884244

申请日：2022-08-09

申请人： Intel Corporation

发明人： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC分类号： G06F9/50 ,  G06F9/46 ,  G06F9/48

摘要： A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20230042934A1

公开(公告)日：2023-02-09

申请号：US17560170

申请日：2021-12-22

申请人： Intel Corporation

发明人： Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Sanjay KUMAR ,  Rajesh SANKARAN ,  Narayan RANGANATHAN ,  Saurabh GAYEN ,  Dhananjay JOSHI ,  Nikhil P. RAO

IPC分类号： G06F11/07

摘要： Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.